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path: root/lib/Target/ARM/Thumb1FrameLowering.cpp
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* Add an MF argument to MI::copyImplicitOps().Jakob Stoklund Olesen2012-12-20
| | | | | | | | | This function is often used to decorate dangling instructions, so a context reference is required to allocate memory for the operands. Also add a corresponding MachineInstrBuilder method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170797 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-04
| | | | | | size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't forget to transfer implicit uses of return instruction.Evan Cheng2012-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147752 91177308-0d34-0410-b5e6-96231b3b80d8
* Copy implicit defs (e.g. r0) when changing tBX_RET to tPOP_RET. This bug isEvan Cheng2012-01-07
| | | | | | | | exposed with an upcoming change will would delete the copy to return register because there is no use! It's amazing anything works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147715 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix more places which should be checking for iOS, not darwin.Evan Cheng2012-01-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147513 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(Chad Rosier2011-10-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142557 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for dynamic stack realignment when in thumb1 mode.Chad Rosier2011-10-18
| | | | | | | rdar://10288916 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142337 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb1 does not support dynamic stack realignment.Chad Rosier2011-10-15
| | | | | | | | | | | rdar://10288916 is tracking this fix. In the past, instcombine and other passes were promoting alloca alignment past the natural alignment, resulting in dynamic stack realignment. Lang's work now prevents this from happening (LLVM commit r141599). Now that this really shouldn't happen report a fatal error rather than silently generate bad code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142028 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."Chad Rosier2011-10-01
| | | | | | to appease nightly testers. Not quite there yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140953 91177308-0d34-0410-b5e6-96231b3b80d8
* Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact Chad Rosier2011-10-01
| | | | | | | | useful if an optimization assumes the stack has been realigned. Credit to Eli for his assistance. rdar://10043857 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140924 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up a few 80 column violations.Jim Grosbach2011-09-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139636 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-24
| | | | | | | | | | Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
* Make tBX_RET and tBX_RET_vararg predicable.Jim Grosbach2011-07-08
| | | | | | | | | | | The normal tBX instruction is predicable, so there's no reason the pseudos for using it as a return shouldn't be. Gives us some nice code-gen improvements as can be seen by the test changes. In particular, several tests now have to disable if-conversion because it works too well and defeats the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134746 91177308-0d34-0410-b5e6-96231b3b80d8
* Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-30
| | | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-30
| | | | | | | | | | Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor away tSpill and tRestore pseudos in ARM backend.Jim Grosbach2011-06-29
| | | | | | | | | The tSpill and tRestore instructions are just copies of the tSTRspi and tLDRspi instructions, respectively. Just use those directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134092 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix coordination for using R4 in Thumb1 as a scratch for SP restore.Jim Grosbach2011-06-13
| | | | | | | | | | The logic for reserving R4 for use as a scratch needs to match that for actually using it. Also, it's not necessary for immediate <=508, so adjust the value checked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132934 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement frame unwinding information emission for Thumb1. Not finished yet ↵Anton Korobeynikov2011-03-05
| | | | | | because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127104 91177308-0d34-0410-b5e6-96231b3b80d8
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-05
| | | | | | | This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach frame lowering to ignore debug values after the terminators.Jakob Stoklund Olesen2011-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123399 91177308-0d34-0410-b5e6-96231b3b80d8
* Even if we don't have 7 bytes of stack space we may need to save andEric Christopher2011-01-11
| | | | | | | | | restore the stack pointer from the frame pointer on thumbv6. Fixes rdar://8819685 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123196 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-10
and fixes here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
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