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path: root/lib/Target/Mips/MipsSEInstrInfo.cpp
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* [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-06-12
| | | | | | | | | | | | | | | | | | | | | | FP64 Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210771 91177308-0d34-0410-b5e6-96231b3b80d8
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207197 91177308-0d34-0410-b5e6-96231b3b80d8
* Implementation of 16-bit microMIPS instructions MFHI and MFLO.Zoran Jovanovic2014-04-03
| | | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D3141 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205532 91177308-0d34-0410-b5e6-96231b3b80d8
* Implementation of microMIPS 16-bit instructions MOVE and JALR.Zoran Jovanovic2014-03-20
| | | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D3112 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204325 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][fp64] Add an implicit def to MTHC1 claiming that it reads the lower ↵Daniel Sanders2014-03-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 32-bits of 64-bit FPR Summary: This is a white lie to workaround a widespread bug in the -mfp64 implementation. The problem is that none of the 32-bit fpu ops mention the fact that they clobber the upper 32-bits of the 64-bit FPR. This allows MTHC1 to be scheduled on the wrong side of most 32-bit FPU ops, particularly MTC1. Fixing that requires a major overhaul of the FPU implementation which can't be done right now due to time constraints. The testcase is SingleSource/Benchmarks/Misc/oourafft.c when given TARGET_CFLAGS='-mips32r2 mfp64 -mmsa'. Also correct the comment added in r203464 to indicate that two instructions were affected. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3029 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203659 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][fp64] Add an implicit def to MFHC1 claiming that it reads the lower ↵Daniel Sanders2014-03-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 32-bits of 64-bit FPR Summary: This is a white lie to workaround a widespread bug in the -mfp64 implementation. The problem is that none of the 32-bit fpu ops mention the fact that they clobber the upper 32-bits of the 64-bit FPR. This allows MFHC1 to be scheduled on the wrong side of most 32-bit FPU ops. Fixing that requires a major overhaul of the FPU implementation which can't be done right now due to time constraints. MFHC1 is one of two affected instructions. These instructions are the only FPU instructions that don't read or write the lower 32-bits. We therefore pretend that it reads the bottom 32-bits to artificially create a dependency and prevent the scheduler changing the behaviour of the code. The other instruction is MTHC1 which will be fixed once I've have found a failing test case for it. The testcase is test-suite/SingleSource/UnitTests/Vector/simple.c when given TARGET_CFLAGS="-mips32r2 -mfp64 -mmsa". Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2966 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203464 91177308-0d34-0410-b5e6-96231b3b80d8
* [C++11] Replace llvm::tie with std::tie.Benjamin Kramer2014-03-02
| | | | | | The old implementation is no longer needed in C++11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202644 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code ↵Daniel Sanders2013-11-18
| | | | | | | | | | | | for (ConstantFP 0.0) Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64 which resulted in an impossible constraint on the register allocation. It now uses BuildPairF64_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195007 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define a pseudo instruction which writes to both the lower and higherAkira Hatanaka2013-10-15
| | | | | | | | parts of the accumulators and gets expanded post-RA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192667 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix definition of mfhi and mflo instructions to read from the wholeAkira Hatanaka2013-10-07
| | | | | | | | | | | | | | | | | accumulator instead of its sub-registers, $hi and $lo. We need this change to prevent a mflo following a mtlo from reading an unpredictable/undefined value, as shown in the following example: mult $6, $7 // result of $6 * $7 is written to $lo and $hi. mflo $2 // read lower 32-bit result from $lo. mtlo $4 // write to $lo. the content of $hi becomes unpredictable. mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value. I don't have a test case for this change that reliably reproduces the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for MSA registers to copyPhysRegDaniel Sanders2013-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191512 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index doubleAkira Hatanaka2013-09-07
| | | | | | | | | | | precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added cfcmsa, and ctcmsaDaniel Sanders2013-08-28
| | | | | | | | | The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189468 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added spill/reload supportDaniel Sanders2013-08-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189332 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add support for mfhc1 and mthc1.Akira Hatanaka2013-08-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188848 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define register class FGRH32 for the high half of the 64-bit floatingAkira Hatanaka2013-08-20
| | | | | | | | | | point registers. We will need this register class later when we add definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Resolve register classes dynamically using ptr_rc to reduce the number ofAkira Hatanaka2013-08-20
| | | | | | | | | | load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename HIRegs and LORegs.Akira Hatanaka2013-08-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename accumulator register classes and FP register operands.Akira Hatanaka2013-08-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use ADDu instead of OR to copy general purpose registers. Also, deleteAkira Hatanaka2013-07-22
| | | | | | | | | the InstAlias pattern which maps "move" to OR to resolve ambiguity in MatchTable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.Akira Hatanaka2013-07-19
| | | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186642 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use function TargetInstrInfo::getRegClass.Akira Hatanaka2013-06-11
| | | | | | | No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183767 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use a helper function which compares the size of the source andAkira Hatanaka2013-06-08
| | | | | | | | | destination operands of an instruction. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183596 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-07
| | | | | | | the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix instruction selection pattern for sint_to_fp node to avoid ↵Akira Hatanaka2013-05-16
| | | | | | | | | | | | | | | | | | | | emitting an invalid instruction sequence. Rather than emitting an int-to-FP move instruction and an int-to-FP conversion instruction during instruction selection, we emit a pseudo instruction which gets expanded post-RA. Without this change, register allocation can possibly insert a floating point register move instruction between the two instructions, which is not valid according to the ISA manual. mtc1 $f4, $4 # int-to-fp move instruction. mov.s $f2, $f4 # move contents of $f4 to $f2. cvt.s.w $f0, $f2 # int-to-fp conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182042 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add option -mno-ldc1-sdc1.Akira Hatanaka2013-05-13
| | | | | | | | | This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename functions. No functionality changes.Akira Hatanaka2013-05-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181713 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Handle reading, writing or copying of ccond field of DSP controlAkira Hatanaka2013-05-02
| | | | | | | | | | | | | register. - Define pseudo instructions which store or load ccond field of the DSP control register. - Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack. - Expand the pseudos before callee-scan save. - Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix handling of instructions which copy to/from accumulator registers.Akira Hatanaka2013-04-30
| | | | | | | | | | | Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Small update to the implementation of eh.return for Mips.Akira Hatanaka2013-04-02
| | | | | | | | | | | This patch initializes t9 to the handler address, but only if the relocation model is pic. This handles the case where handler to which eh.return jumps points to the start of the function. Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178588 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix MipsSEInstrInfo::copyPhysReg, loadRegFromStack and storeRegToStackAkira Hatanaka2013-03-30
| | | | | | | to handle accumulator registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178392 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.Akira Hatanaka2013-03-29
| | | | | | | No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178327 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Lower EH_RETURN.Akira Hatanaka2013-01-30
| | | | | | | Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173862 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copyAkira Hatanaka2012-12-20
| | | | | | | | | | | | physical register $r1 to $r0. GNU disassembler recognizes an "or" instruction as a "move", and this change makes the disassembled code easier to read. Original patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170655 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-03
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Stop reserving register AT and use register scavenger when a scratchAkira Hatanaka2012-11-03
| | | | | | | | register is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167341 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Delete MipsFunctionInfo::EmitNOAT. Unconditionally print directiveAkira Hatanaka2012-11-02
| | | | | | | | | "set .noat" so that the assembler doesn't issue warnings when register $AT is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167310 91177308-0d34-0410-b5e6-96231b3b80d8
* Make function loadImmediate a member of MipsSEInstrInfo and change it to returnAkira Hatanaka2012-08-23
| | | | | | | | | | | | the temporary register that was used to load the immediate. Currently, it always returns register $at, but this will change if, in the future, we decide to use another register. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162417 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the code that creates instances of MipsInstrInfo and MipsFrameLowering outAkira Hatanaka2012-08-02
| | | | | | | | of MipsTargetMachine.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161191 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emitsAkira Hatanaka2012-07-31
| | | | | | | | | instructions that decrement and increment the stack pointer before and after a call when the function does not have a reserved call frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161093 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo andAkira Hatanaka2012-07-31
| | | | | | | | MipsSERegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161092 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),Akira Hatanaka2012-07-31
and MipsSEInstrInfo (for mips32/64). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161081 91177308-0d34-0410-b5e6-96231b3b80d8
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