| Commit message (Expand) | Author | Age |
|---|
| * | Replace the SubRegSet tablegen class with a less error-prone mechanism. | Jakob Stoklund Olesen | 2010-05-26 |
| * | Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." | Jakob Stoklund Olesen | 2010-05-26 |
| * | Replace the SubRegSet tablegen class with a less error-prone mechanism. | Jakob Stoklund Olesen | 2010-05-26 |
| * | Remove NumberHack entirely. | Jakob Stoklund Olesen | 2010-05-25 |
| * | Switch SubRegSet to using symbolic SubRegIndices | Jakob Stoklund Olesen | 2010-05-24 |
| * | Replace the tablegen RegisterClass field SubRegClassList with an alist-like data | Jakob Stoklund Olesen | 2010-05-24 |
| * | Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are | Jakob Stoklund Olesen | 2010-05-24 |
| * | Really reserve R2 on PPC Darwin. PR 6314. | Dale Johannesen | 2010-02-16 |
| * | Model the carry bit on ppc32. Without this we could | Dale Johannesen | 2009-09-18 |
| * | Add support for the PowerPC 64-bit SVR4 ABI. | Tilmann Scheller | 2009-08-15 |
| * | Various small changes related to the Condition Register on PowerPC. | Tilmann Scheller | 2009-07-03 |
| * | Refactor ABI code in the PowerPC backend. | Tilmann Scheller | 2009-07-03 |
| * | Implement the SVR4 ABI for PowerPC. | Tilmann Scheller | 2009-07-03 |
| * | Add a RM pseudoreg for the rounding mode, which | Dale Johannesen | 2008-10-29 |
| * | Clean up PPC register specification. | Evan Cheng | 2008-07-07 |
| * | Tail call optimization improvements: | Arnold Schwaighofer | 2008-04-30 |
| * | Add description of individual bits in CR. This fix PR1765. | Nicolas Geoffray | 2008-03-10 |
| * | Rename PrintableName to Name. | Bill Wendling | 2008-02-26 |
| * | Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool | Bill Wendling | 2008-02-26 |
| * | Some platforms use the same name for 32-bit and 64-bit registers (like | Bill Wendling | 2008-02-24 |
| * | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner | 2007-12-29 |
| * | Use TableGen to emit information for dwarf register numbers. | Anton Korobeynikov | 2007-11-11 |
| * | R0 is a sub-register of X0, etc. | Evan Cheng | 2007-05-08 |
| * | llvm bug #1350, parts 1, 2, and 3. | Nate Begeman | 2007-05-01 |
| * | We'd still like to register allocate r2 on darwin before the callee-save | Nate Begeman | 2007-01-29 |
| * | Changes from Nick Lewycky with a simplified PPCTargetAsmInfo. | Jim Laskey | 2006-12-21 |
| * | in ppc64-mode, don't allocate the 32-bit version of r13 either. | Chris Lattner | 2006-11-20 |
| * | r13 is the thread pointer on darwin/ppc64, don't allocate it. | Chris Lattner | 2006-11-20 |
| * | This is a general clean up of the PowerPC ABI. Address several problems and | Jim Laskey | 2006-11-16 |
| * | Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls | Chris Lattner | 2006-11-14 |
| * | Constify some methods. Patch provided by Anton Vayvod, thanks! | Chris Lattner | 2006-08-17 |
| * | Remove the -darwin and -aix llc options, inferring darwinism and aixism from | Chris Lattner | 2006-06-16 |
| * | Revert Nate's CR patch from last night, which caused many regressions (e.g. f... | Chris Lattner | 2006-05-04 |
| * | Since we don't handle callee-save CRs right yet, don't allocate them. Also | Nate Begeman | 2006-05-02 |
| * | Prefer to allocate V2-V5 before V0,V1. This lets us generate code like this: | Chris Lattner | 2006-04-17 |
| * | add all supported formats to the vector register file | Chris Lattner | 2006-03-25 |
| * | Add dwarf register numbering to register data. | Jim Laskey | 2006-03-24 |
| * | Claim to have v16i8 for perm masks | Chris Lattner | 2006-03-20 |
| * | For functions that use vector registers, save VRSAVE, mark used | Chris Lattner | 2006-03-13 |
| * | Bye bye HACKTROCITY. | Evan Cheng | 2005-12-22 |
| * | Pattern-match return. Includes gross hack! | Nate Begeman | 2005-12-20 |
| * | Add a second vector type to the VRRC register class, and fix some patterns | Nate Begeman | 2005-12-16 |
| * | Support multiple ValueTypes per RegisterClass, needed for upcoming vector | Nate Begeman | 2005-12-01 |
| * | Cosmetic change, better reflects actual values | Nate Begeman | 2005-12-01 |
| * | Add the majority of the vector machien value types we expect to support, | Nate Begeman | 2005-11-29 |
| * | don't say this is i128, because it isn't yet. Hopefully nate will change | Chris Lattner | 2005-11-29 |
| * | Small tweaks noticed while on the plane. | Nate Begeman | 2005-11-26 |
| * | Some first bits of AltiVec stuff: Instruction Formats, Encodings, and | Nate Begeman | 2005-11-23 |
| * | apply some tblgen majik to simplify the X register definitions | Chris Lattner | 2005-10-19 |
| * | Make a new reg class for 64 bit regs that aliases the 32 bit regs. This | Nate Begeman | 2005-10-19 |
