index
:
llvm
embtk-support-master
embtk-support-release-3.2
embtk-support-release-3.3
embtk-support-release-3.4
master
release-3.2
release-3.4
Unofficial llvm GIT mirror used in EmbToolkit
Git daemon user
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
lib
/
Target
/
R600
/
R600InstrInfo.cpp
Commit message (
Expand
)
Author
Age
*
R600: Use LDS and vectors for private memory
Tom Stellard
2014-06-17
*
R600: Remove AMDIL instruction and register definitions
Tom Stellard
2014-06-13
*
R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget
Tom Stellard
2014-06-13
*
R600: Drop use of cached TargetMachine in R600InstrInfo.cpp
Tom Stellard
2014-06-13
*
[C++] Use 'nullptr'. Target edition.
Craig Topper
2014-04-25
*
[cleanup] Lift using directives, DEBUG_TYPE definitions, and even some
Chandler Carruth
2014-04-22
*
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.
Benjamin Kramer
2014-03-02
*
R600: Remove successive JUMP in AnalyzeBranch when AllowModify is true
Tom Stellard
2014-01-23
*
R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()
Tom Stellard
2013-11-22
*
[weak vtables] Remove a bunch of weak vtables
Juergen Ributzka
2013-11-19
*
Revert r194865 and r194874.
Alexey Samsonov
2013-11-18
*
R600: Make dot_4 instructions predicable
Vincent Lejeune
2013-11-16
*
[weak vtables] Remove a bunch of weak vtables
Juergen Ributzka
2013-11-15
*
R600: Fix scheduling of instructions that use the LDS output queue
Tom Stellard
2013-11-15
*
R600/SI: Add support for private address space load/store
Tom Stellard
2013-11-13
*
R600: Simplify handling of private address space
Tom Stellard
2013-10-22
*
R600: Remove unused InstrInfo::getMovImmInstr() function
Tom Stellard
2013-10-22
*
R600: add a pass that merges clauses.
Vincent Lejeune
2013-10-01
*
R600: Enable -verify-machineinstrs in some tests.
Vincent Lejeune
2013-10-01
*
IfConverter: Use TargetSchedule for instruction latencies
Arnold Schwaighofer
2013-09-30
*
R600: Don't use trans slot for instructions that read LDS source registers
Tom Stellard
2013-09-12
*
R600: Use shared op optimization when checking cycle compatibility
Vincent Lejeune
2013-09-04
*
R600: Non vector only instruction can be scheduled on trans unit
Vincent Lejeune
2013-09-04
*
R600: Use SchedModel enum for is{Trans,Vector}Only functions
Vincent Lejeune
2013-09-04
*
R600: Add support for i8 and i16 local memory stores
Tom Stellard
2013-08-26
*
R600: Add IsExport bit to TableGen instruction definitions
Tom Stellard
2013-08-16
*
R600: Add 64-bit float load/store support
Tom Stellard
2013-08-01
*
Revert "R600: Non vector only instruction can be scheduled on trans unit"
Tom Stellard
2013-07-31
*
Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
Tom Stellard
2013-07-31
*
R600: Avoid more than 4 literals in the same instruction group at scheduling
Vincent Lejeune
2013-07-31
*
R600: Non vector only instruction can be scheduled on trans unit
Vincent Lejeune
2013-07-31
*
R600: Use SchedModel enum for is{Trans,Vector}Only functions
Vincent Lejeune
2013-07-31
*
R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()
Tom Stellard
2013-07-23
*
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector s...
Craig Topper
2013-07-14
*
Replacing an empty switch with its moral equivalent. No functional changes i...
Aaron Ballman
2013-07-10
*
R600: Do not predicated basic block with multiple alu clause
Vincent Lejeune
2013-07-09
*
R600: Fix an unitialized variable in R600InstrInfo.cpp
Vincent Lejeune
2013-06-30
*
R600: Unbreak GCC build.
Benjamin Kramer
2013-06-29
*
R600: Support schedule and packetization of trans-only inst
Vincent Lejeune
2013-06-29
*
R600: Bank Swizzle now display SCL equivalent
Vincent Lejeune
2013-06-29
*
R600: Add local memory support via LDS
Tom Stellard
2013-06-28
*
R600: Add support for GROUP_BARRIER instruction
Tom Stellard
2013-06-28
*
R600: Add ALUInst bit to tablegen definitions v2
Tom Stellard
2013-06-28
*
R600: Use new getNamedOperandIdx function generated by TableGen
Tom Stellard
2013-06-25
*
R600: PV stores Reg id, not index
Vincent Lejeune
2013-06-17
*
R600: Rework subtarget info and remove AMDILDevice classes
Tom Stellard
2013-06-07
*
Don't cache the instruction and register info from the TargetMachine, because
Bill Wendling
2013-06-07
*
R600: Make sure to schedule AR register uses and defs in the same clause
Tom Stellard
2013-06-05
*
R600: Const/Neg/Abs can be folded to dot4
Vincent Lejeune
2013-06-04
*
Move passes from namespace llvm into anonymous namespaces. Sort includes whil...
Benjamin Kramer
2013-05-23
[next]