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	Commit message (Expand)	Author	Age
*	R600: Allow ftrunc	Tom Stellard	2013-12-20
*	R600: Workaround for cayman loop bug	Vincent Lejeune	2013-12-02
*	R600: Add support for ISD::FROUND	Tom Stellard	2013-11-27
*	R600/SI: Fixing handling of condition codes	Tom Stellard	2013-11-22
*	R600/SI: Add support for private address space load/store	Tom Stellard	2013-11-13
*	R600: Use function inputs to represent data stored in gpr	Vincent Lejeune	2013-11-11
*	R600: Clear the VPM bit of export instructions.	Vincent Lejeune	2013-10-13
*	R600: Add a ldptr intrinsic to support MSAA.	Vincent Lejeune	2013-10-02
*	R600: add a pass that merges clauses.	Vincent Lejeune	2013-10-01
*	R600: Enable -verify-machineinstrs in some tests.	Vincent Lejeune	2013-10-01
*	R600: Fix handling of NAN in comparison instructions	Tom Stellard	2013-09-28
*	SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()	Tom Stellard	2013-09-28
*	R600: Add support for LDS atomic subtract	Aaron Watry	2013-09-06
*	R600: Add support for local memory atomic add	Tom Stellard	2013-09-05
*	R600: Use SchedModel enum for is{Trans,Vector}Only functions	Vincent Lejeune	2013-09-04
*	R600: Add support for i8 and i16 local memory loads	Tom Stellard	2013-08-26
*	R600: Add support for i8 and i16 local memory stores	Tom Stellard	2013-08-26
*	R600: Add support for i16 and i8 global stores	Tom Stellard	2013-08-16
*	R600: Add support for v4i32 stores on Cayman	Tom Stellard	2013-08-16
*	R600: Add IsExport bit to TableGen instruction definitions	Tom Stellard	2013-08-16
*	R600: Change the RAT instruction assembly names so they match the docs	Tom Stellard	2013-08-16
*	R600/SI: Handle MSAA texture targets	Tom Stellard	2013-08-14
*	R600: Add 64-bit float load/store support	Tom Stellard	2013-08-01
*	Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"	Tom Stellard	2013-07-31
*	R600: Use SchedModel enum for is{Trans,Vector}Only functions	Vincent Lejeune	2013-07-31
*	R600: Remove predicated_break inst	Vincent Lejeune	2013-07-31
*	R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessary	Tom Stellard	2013-07-23
*	R600: Add support for 24-bit MAD instructions	Tom Stellard	2013-07-23
*	R600: Add support for 24-bit MUL instructions	Tom Stellard	2013-07-23
*	R600: Improve support for < 32-bit loads	Tom Stellard	2013-07-23
*	R600: Use KCache for kernel arguments	Tom Stellard	2013-07-23
*	R600: Clean up extended load patterns	Tom Stellard	2013-07-23
*	R600: Don't emit empty then clause and use alu_pop_after	Vincent Lejeune	2013-07-19
*	R600: Do not predicated basic block with multiple alu clause	Vincent Lejeune	2013-07-09
*	R600: Use DAG lowering pass to handle fcos/fsin	Vincent Lejeune	2013-07-09
*	R600: Print Export Swizzle	Vincent Lejeune	2013-07-09
*	R600: Support schedule and packetization of trans-only inst	Vincent Lejeune	2013-06-29
*	R600: Add local memory support via LDS	Tom Stellard	2013-06-28
*	R600: Add support for GROUP_BARRIER instruction	Tom Stellard	2013-06-28
*	R600: Add ALUInst bit to tablegen definitions v2	Tom Stellard	2013-06-28
*	R600: Use new getNamedOperandIdx function generated by TableGen	Tom Stellard	2013-06-25
*	R600: Add support for i32 loads from the constant address space on Cayman	Tom Stellard	2013-06-25
*	R600: Fix spelling error in comment	Aaron Watry	2013-06-24
*	R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.	Vincent Lejeune	2013-06-17
*	R600: Use correct encoding for Vertex Fetch instructions on Cayman	Tom Stellard	2013-06-14
*	R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman	Tom Stellard	2013-06-14
*	R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class	Tom Stellard	2013-06-14
*	R600: Move instruction encoding definitions into a separate .td file	Tom Stellard	2013-06-14
*	R600: Rework subtarget info and remove AMDILDevice classes	Tom Stellard	2013-06-07
*	R600: Constraints input regs of interp_xy,_zw	Vincent Lejeune	2013-06-03