| Commit message (Expand) | Author | Age |
|---|
| * | Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ... | Craig Topper | 2014-02-02 |
| * | Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field i... | Craig Topper | 2014-02-02 |
| * | [x86] Fix signed relocations for i64i32imm operands | David Woodhouse | 2014-01-30 |
| * | [x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385) | David Woodhouse | 2014-01-22 |
| * | [x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385) | David Woodhouse | 2014-01-22 |
| * | ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385) | David Woodhouse | 2014-01-22 |
| * | [x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385) | David Woodhouse | 2014-01-22 |
| * | [x86] Allow address-size overrides for STOS[BWLQ] (PR9385) | David Woodhouse | 2014-01-22 |
| * | [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) | David Woodhouse | 2014-01-22 |
| * | [x86] Rename MOVSD/STOSD/LODSD/OUTSD to MOVSL/STOSL/LODSL/OUTSL | David Woodhouse | 2014-01-20 |
| * | Allow x86 mov instructions to/from memory with absolute address to be encoded... | Craig Topper | 2014-01-16 |
| * | [x86] Fix retq/retl handling in 64-bit mode | David Woodhouse | 2014-01-13 |
| * | [x86] Do not relax PUSHi16 to PUSHi32 (PR18414) | David Woodhouse | 2014-01-08 |
| * | [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand | David Woodhouse | 2014-01-08 |
| * | [x86] Disambiguate RET[QL] and fix aliases for 16-bit mode | David Woodhouse | 2014-01-08 |
| * | [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases | David Woodhouse | 2014-01-08 |
| * | [x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliases | David Woodhouse | 2014-01-08 |
| * | [x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode | David Woodhouse | 2014-01-08 |
| * | [x86] Add OpSize16 to instructions that need it | David Woodhouse | 2014-01-08 |
| * | [x86] Add basic support for .code16 | Craig Topper | 2014-01-06 |
| * | Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack. | Craig Topper | 2014-01-05 |
| * | Add a new x86 specific instruction flag to force some isCodeGenOnly instructi... | Craig Topper | 2014-01-05 |
| * | Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the correspond... | Craig Topper | 2014-01-05 |
| * | Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr. | Craig Topper | 2014-01-02 |
| * | AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp | Elena Demikhovsky | 2014-01-01 |
| * | [x86] Rename In32BitMode predicate to Not64BitMode | Eric Christopher | 2013-12-20 |
| * | AVX-512: Added legal type MVT::i1 and VK1 register for it. | Elena Demikhovsky | 2013-12-16 |
| * | AVX-512: Removed "z" suffix from AVX-512 instructions, since it is incompatib... | Elena Demikhovsky | 2013-12-11 |
| * | Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar, | Yunzhong Gao | 2013-10-16 |
| * | Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instru... | Craig Topper | 2013-10-14 |
| * | AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics. | Elena Demikhovsky | 2013-10-09 |
| * | Remove underscores from TBM instruction names for consistency with other inst... | Craig Topper | 2013-10-05 |
| * | Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are... | Craig Topper | 2013-10-05 |
| * | Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (... | Craig Topper | 2013-10-05 |
| * | Add XOP disassembler support. Fixes PR13933. | Craig Topper | 2013-10-03 |
| * | Add patterns for selecting TBM instructions from logical operations. Patch fr... | Craig Topper | 2013-10-03 |
| * | BEXTR should be defined to take same type for bother operands. | Craig Topper | 2013-10-01 |
| * | Adding intrinsics to the llvm backend for TBM instruction set. | Yunzhong Gao | 2013-09-27 |
| * | Adds support for Atom Silvermont (SLM) - -march=slm | Preston Gurd | 2013-09-13 |
| * | Partial support for Intel SHA Extensions (sha1rnds4) | Ben Langmuir | 2013-09-12 |
| * | Add neverHasSideEffects=1 on a couple move instructions. | Craig Topper | 2013-09-08 |
| * | Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fix... | Craig Topper | 2013-09-02 |
| * | Fixup BZHI selection to remove an unneeded zero extension. | Craig Topper | 2013-08-30 |
| * | Remove unused X86andn_flag node. | Craig Topper | 2013-08-30 |
| * | Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, ... | Craig Topper | 2013-08-30 |
| * | Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides... | Craig Topper | 2013-08-26 |
| * | Put some of the AVX-512 parsing stuff in a more consistent place with the exi... | Craig Topper | 2013-08-25 |
| * | First round of fixes for the x86 fixes for the x86 move accumulator from/to m... | Craig Topper | 2013-08-25 |
| * | Add hasSideEffects/mayLoad/mayStore flags to the X86 moffs8/moffs16/moffs32/m... | Craig Topper | 2013-08-24 |
| * | Remove trailing whitespace. | Craig Topper | 2013-08-24 |
