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path: root/lib/Target/X86/X86InstrInfo.td
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* Reverting r56249. On further investigation, this functionality isn't needed.Bill Wendling2008-09-16
| | | | | | | Apologies for the thrashing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
* - Change "ExternalSymbolSDNode" to "SymbolSDNode".Bill Wendling2008-09-16
| | | | | | | | | | | - Add linkage to SymbolSDNode (default to external). - Change ISD::ExternalSymbol to ISD::Symbol. - Change ISD::TargetExternalSymbol to ISD::TargetSymbol These changes pave the way to allowing SymbolSDNodes with non-external linkage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-12
| | | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
* Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 ↵Evan Cheng2008-08-30
| | | | | | shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55558 91177308-0d34-0410-b5e6-96231b3b80d8
* Split the ATOMIC NodeType's to include the size, e.g.Dale Johannesen2008-08-28
| | | | | | | | | | | | | | | | | | ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD. Increased the Hardcoded Constant OpActionsCapacity to match. Large but boring; no functional change. This is to support partial-word atomics on ppc; i8 is not a valid type there, so by the time we get to lowering, the ATOMIC_LOAD nodes looks the same whether the type was i8 or i32. The information can be added to the AtomicSDNode, but that is the largest SDNode; I don't fully understand the SDNode allocation, but it is sensitive to the largest node size, so increasing that must be bad. This is the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55457 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting r55190, r55191, and r55192. They broke the build with this error ↵Bill Wendling2008-08-22
| | | | | | | | | | | | | | | | | message: {standard input}:17:bad register name `%sil' make[4]: *** [libgcc/./_addvsi3.o] Error 1 make[4]: *** Waiting for unfinished jobs.... {standard input}:23:bad register name `%dil' {standard input}:28:bad register name `%dil' make[4]: *** [libgcc/./_addvdi3.o] Error 1 {standard input}:18:bad register name `%sil' make[4]: *** [libgcc/./_subvsi3.o] Error 1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55200 91177308-0d34-0410-b5e6-96231b3b80d8
* Anyext tweaks for x86. When extloading a value to i32 or i64, chooseDan Gohman2008-08-22
| | | | | | | | | instructions that define the full 32 or 64-bit value. When anyexting from i8 to i16 or i32, it's not necessary to zero out the high portion of the register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55190 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATEDan Gohman2008-08-20
| | | | | | | | | | | | | | out of X86ISelDAGToDAG.cpp C++ code and into tablegen code. Among other things, using tablegen for these things makes them friendlier to FastISel. Tablegen can handle the case of i8 subregs on x86-32, but currently the C++ code for that case uses MVT::Flag in a tricky way, and it happens to schedule better in some cases. So for now, leave the C++ code in place to handle the i8 case on x86-32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55078 91177308-0d34-0410-b5e6-96231b3b80d8
* Tablegen generated code already tests the opcode value, so it's notDan Gohman2008-08-20
| | | | | | | necessary to use dyn_cast in these predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55055 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic.Bill Wendling2008-08-20
| | | | | | | Just expand it like the other X-bit sub_and_fetches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55023 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the __sync_sub_and_fetch atomics and friends for X86. The codeBill Wendling2008-08-19
| | | | | | | | was already present, but not hooked up to anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55018 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 8 and 16 bit forms of __syncDale Johannesen2008-08-19
| | | | | | | | | | | | builtins on X86. Change "lock" instructions to be on a separate line. This is needed to work around a bug in the Darwin assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54999 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-introduce the 8-bit subreg zext-inreg patterns for x86-32,Dan Gohman2008-08-06
| | | | | | | | this time using MOV32to32_ and MOV16to16_. Thanks to Evan for suggesting this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54418 91177308-0d34-0410-b5e6-96231b3b80d8
* xchg does not modify FLAGS.Dan Gohman2008-08-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54411 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r54147 with a constraint to only use the 8-bitDan Gohman2008-07-30
| | | | | | | | | | | | subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54223 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 54147.Dan Gohman2008-07-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54148 91177308-0d34-0410-b5e6-96231b3b80d8
* Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation,Dan Gohman2008-07-28
| | | | | | | | | which is represented in codegen as an 'and' operation. This matches them with movz instructions, instead of leaving them to be matched by and instructions with an immediate field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54147 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding of atomic compare and swap for i64Anton Korobeynikov2008-07-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53911 91177308-0d34-0410-b5e6-96231b3b80d8
* Added MemOperands to Atomic operations since Atomics touches memory.Mon P Wang2008-06-25
| | | | | | | | | Added abstract class MemSDNode for any Node that have an associated MemOperand Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and atomic.lss => atomic.load.sub git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
* XOR32rr, etc. are not AsCheapAsMove, but MOV32ri, etc. are.Evan Cheng2008-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52454 91177308-0d34-0410-b5e6-96231b3b80d8
* add missing atomic intrinsic from gccAndrew Lenharth2008-06-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52270 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the DAGISelEmitter to not compute the variable_ops operandDan Gohman2008-05-31
| | | | | | | | | | | | index for the input pattern in terms of the output pattern. Instead keep track of how many fixed operands the input pattern actually has, and have the input matching code pass the output-emitting function that index value. This simplifies the code, disentangles variables_ops from the support for predication operations, and makes variable_ops more robust. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51808 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for CALL32m and CALL64m. They aren't matched in mostDan Gohman2008-05-29
| | | | | | | | | | | | | cases due to an isel deficiency already noted in lib/Target/X86/README.txt, but they can be matched in this fold-call.ll testcase, for example. This is interesting mainly because it exposes a tricky tblgen bug; tblgen was incorrectly computing the starting index for variable_ops in the case of a complex pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51706 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a tblgen problem handling variable_ops in tblgen instructionDan Gohman2008-05-29
| | | | | | | | | | | | | definitions. This adds a new construct, "discard", for indicating that a named node in the input matching pattern is to be discarded, instead of corresponding to a node in the output pattern. This allows tblgen to know where the arguments for the varaible_ops are supposed to begin. This fixes "rdar://5791600", whatever that is ;-). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51699 91177308-0d34-0410-b5e6-96231b3b80d8
* XOR?RI instructions aren't as cheap as moves.Bill Wendling2008-05-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51664 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and theBill Wendling2008-05-29
| | | | | | | like. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51662 91177308-0d34-0410-b5e6-96231b3b80d8
* Doh. Alignment is in bytes, not in bits.Evan Cheng2008-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51092 91177308-0d34-0410-b5e6-96231b3b80d8
* - Fix the pasto in the fix for a previous pasto.Evan Cheng2008-05-13
| | | | | | | - Incorporate Chris' comment suggestion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51061 91177308-0d34-0410-b5e6-96231b3b80d8
* - Don't treat anyext 16-bit load as a 32-bit load if it's volatile.Evan Cheng2008-05-13
| | | | | | | - Correct a pasto. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51054 91177308-0d34-0410-b5e6-96231b3b80d8
* On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for ↵Evan Cheng2008-05-13
| | | | | | i8 anyext load to i16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51019 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a copy+paste bug; pseudo-instructions shouldn't haveDan Gohman2008-05-12
| | | | | | | encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50997 91177308-0d34-0410-b5e6-96231b3b80d8
* Added addition atomic instrinsics and, or, xor, min, and max.Mon P Wang2008-05-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
* Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look ↵Anton Korobeynikov2008-05-04
| | | | | | | | | for tlsaddr pattern), but should work. Work is in progress, more models will follow git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50630 91177308-0d34-0410-b5e6-96231b3b80d8
* Tail call optimization improvements:Arnold Schwaighofer2008-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move platform independent code (lowering of possibly overwritten arguments, check for tail call optimization eligibility) from target X86ISelectionLowering.cpp to TargetLowering.h and SelectionDAGISel.cpp. Initial PowerPC tail call implementation: Support ppc32 implemented and tested (passes my tests and test-suite llvm-test). Support ppc64 implemented and half tested (passes my tests). On ppc tail call optimization is performed if caller and callee are fastcc call is a tail call (in tail call position, call followed by ret) no variable argument lists or byval arguments option -tailcallopt is enabled Supported: * non pic tail calls on linux/darwin * module-local tail calls on linux(PIC/GOT)/darwin(PIC) * inter-module tail calls on darwin(PIC) If constraints are not met a normal call will be emitted. A test checking the argument lowering behaviour on x86-64 was added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller ↵Evan Cheng2008-04-25
| | | | | | type to a larger one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50278 91177308-0d34-0410-b5e6-96231b3b80d8
* xchg which references a memory operand does not need to lock prefix. ↵Evan Cheng2008-04-19
| | | | | | Atomicity is guaranteed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49946 91177308-0d34-0410-b5e6-96231b3b80d8
* - Fix atomic operation JIT encoding.Evan Cheng2008-04-18
| | | | | | | - Remove unused instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49921 91177308-0d34-0410-b5e6-96231b3b80d8
* Also support Intel asm syntax.Evan Cheng2008-04-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49878 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assembly code for atomic operations.Evan Cheng2008-04-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49869 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 col fixNate Begeman2008-04-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49569 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow certain lea instructions to be rematerialized.Evan Cheng2008-03-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48855 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't loose incoming argument registers. Fix documentation style.Arnold Schwaighofer2008-03-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48545 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-15
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of a pseudo instruction and replace it with subreg based operation ↵Christopher Lamb2008-03-13
| | | | | | | | | | on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommitting parts of r48130. These do not appear to cause the observed ↵Christopher Lamb2008-03-11
| | | | | | failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the model for FP Stack return to use fp operands on the Chris Lattner2008-03-11
| | | | | | | | RET instruction instead of using FpSET_ST0_32. This also generalizes the code to handling returning of multiple FP results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48209 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng2008-03-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow insert_subreg into implicit, target-specific values. Christopher Lamb2008-03-10
| | | | | | | | Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
* 64bit CAS on 32bit x86.Andrew Lenharth2008-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47929 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 column violations.Evan Cheng2008-03-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47878 91177308-0d34-0410-b5e6-96231b3b80d8
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