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path: root/lib/Target/X86/X86InstrInfo.td
Commit message (Expand)AuthorAge
* [X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODSCraig Topper2014-02-27
* [X86] Add RAX/EAX/AX Uses/Defs to XCHG RAX/EAX/AX instructions.Craig Topper2014-02-27
* [X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instru...Craig Topper2014-02-27
* Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their ...Craig Topper2014-02-18
* Add an x86 prefix encoding for instructions that would decode to a different ...Craig Topper2014-02-18
* Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.Craig Topper2014-02-15
* [X86] Don't mark movabsq as cheap-as-move - it isn't that cheap.Juergen Ributzka2014-02-14
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-10
* Revert r201059 and r201060.Bob Wilson2014-02-10
* Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' fie...Craig Topper2014-02-10
* Move matching for x86 BMI BLSI/BLSMSK/BLSR instructions to isel patterns inst...Craig Topper2014-02-05
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ...Craig Topper2014-02-02
* Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field i...Craig Topper2014-02-02
* [x86] Fix signed relocations for i64i32imm operandsDavid Woodhouse2014-01-30
* [x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385)David Woodhouse2014-01-22
* [x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385)David Woodhouse2014-01-22
* ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)David Woodhouse2014-01-22
* [x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385)David Woodhouse2014-01-22
* [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse2014-01-22
* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-22
* [x86] Rename MOVSD/STOSD/LODSD/OUTSD to MOVSL/STOSL/LODSL/OUTSLDavid Woodhouse2014-01-20
* Allow x86 mov instructions to/from memory with absolute address to be encoded...Craig Topper2014-01-16
* [x86] Fix retq/retl handling in 64-bit modeDavid Woodhouse2014-01-13
* [x86] Do not relax PUSHi16 to PUSHi32 (PR18414)David Woodhouse2014-01-08
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-08
* [x86] Disambiguate RET[QL] and fix aliases for 16-bit modeDavid Woodhouse2014-01-08
* [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliasesDavid Woodhouse2014-01-08
* [x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliasesDavid Woodhouse2014-01-08
* [x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit modeDavid Woodhouse2014-01-08
* [x86] Add OpSize16 to instructions that need itDavid Woodhouse2014-01-08
* [x86] Add basic support for .code16Craig Topper2014-01-06
* Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.Craig Topper2014-01-05
* Add a new x86 specific instruction flag to force some isCodeGenOnly instructi...Craig Topper2014-01-05
* Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the correspond...Craig Topper2014-01-05
* Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.Craig Topper2014-01-02
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-01
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-20
* AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky2013-12-16
* AVX-512: Removed "z" suffix from AVX-512 instructions, since it is incompatib...Elena Demikhovsky2013-12-11
* Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar,Yunzhong Gao2013-10-16
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instru...Craig Topper2013-10-14
* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-09
* Remove underscores from TBM instruction names for consistency with other inst...Craig Topper2013-10-05
* Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are...Craig Topper2013-10-05
* Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (...Craig Topper2013-10-05
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-03
* Add patterns for selecting TBM instructions from logical operations. Patch fr...Craig Topper2013-10-03
* BEXTR should be defined to take same type for bother operands.Craig Topper2013-10-01
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-27
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-13
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