| Commit message (Expand) | Author | Age |
* | Add the other form of movq xmm,xmm for the disassembler. | Craig Topper | 2014-01-05 |
* | Use patterns to remove some duplicate instructions. | Craig Topper | 2014-01-05 |
* | Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disa... | Craig Topper | 2014-01-05 |
* | Add a new x86 specific instruction flag to force some isCodeGenOnly instructi... | Craig Topper | 2014-01-05 |
* | Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler tabl... | Craig Topper | 2014-01-02 |
* | [x86] Rename In32BitMode predicate to Not64BitMode | Eric Christopher | 2013-12-20 |
* | AVX-512: Added legal type MVT::i1 and VK1 register for it. | Elena Demikhovsky | 2013-12-16 |
* | Added new X86 patterns to select SSE scalar fp arithmetic instructions from | Andrea Di Biagio | 2013-12-12 |
* | Ensure that the backend no longer emits unnecessary vector insert instructions | Andrea Di Biagio | 2013-12-10 |
* | Add an intrinsic for the SSE2 PAUSE instruction. | Cameron McInally | 2013-11-26 |
* | Fix assembly operands for the SSE2 cvtsd2ss instruction. | Cameron McInally | 2013-11-19 |
* | Lift alignment restrictions on load folding for a significant portion of AVX ... | Craig Topper | 2013-11-05 |
* | Fix PR17764 | Michael Liao | 2013-11-02 |
* | X86: Custom lower sext v16i8 to v16i16, and the corresponding truncate. | Benjamin Kramer | 2013-10-23 |
* | X86: Custom lower zext v16i8 to v16i16. | Benjamin Kramer | 2013-10-23 |
* | Replace (V)MOVZDI2PDIrr/rm instructions with patterns that select (V)MOVDI2PD... | Craig Topper | 2013-10-22 |
* | X86 vector element shift-by-immediate instructions take i8 immediates. Make | Lang Hames | 2013-10-21 |
* | Remove x86_sse42_crc32_64_8 intrinsic. It has no functional difference from x... | Craig Topper | 2013-10-15 |
* | Create classes to reduce the size of the tablegen entries for the CRC32 instr... | Craig Topper | 2013-10-14 |
* | Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instru... | Craig Topper | 2013-10-14 |
* | Add disassembler support for SSE4.1 register/register form of PEXTRW. There i... | Craig Topper | 2013-10-14 |
* | Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the ... | Craig Topper | 2013-10-14 |
* | Don't use 64-bit versions of MOVMSKPD in CodeGen. The instructions only produ... | Craig Topper | 2013-10-14 |
* | Mark some more instructions as CodeGenOnly. Remove filters from the disassemb... | Craig Topper | 2013-10-12 |
* | Allow non-AVX form of pmovmskb to take a GR64 operand. | Craig Topper | 2013-10-10 |
* | Remove duplicate instructions. | Craig Topper | 2013-10-10 |
* | AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics. | Elena Demikhovsky | 2013-10-09 |
* | Mark some instructions as CodeGenOnly since they aren't needed by the assembl... | Craig Topper | 2013-10-09 |
* | Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. Thi... | Craig Topper | 2013-10-09 |
* | Remove some instructions that existed to provide aliases to the assembler. Ca... | Craig Topper | 2013-10-08 |
* | Remove some instructions that seem to only exist to trick the filtering check... | Craig Topper | 2013-10-07 |
* | Remove FsMOVAPSrr and friends. They have no patterns and are no longer select... | Craig Topper | 2013-10-07 |
* | Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to registe... | Craig Topper | 2013-10-07 |
* | Switch HasAVX to UseAVX in one spot to ensure that AVX512 form of VINSERTPS i... | Craig Topper | 2013-09-27 |
* | Removal some duplicate patterns. | Craig Topper | 2013-09-27 |
* | Fixing Intel format of the vshufpd instruction. | Yunzhong Gao | 2013-09-27 |
* | Lift alignment restrictions on load/store folding of VEXTRACTI128/VINSERTI128. | Craig Topper | 2013-09-20 |
* | Lift alignment restrictions for load/store folding on VINSERTF128/VEXTRACTF12... | Craig Topper | 2013-09-18 |
* | Add llvm.x86.* intrinsics for Intel SHA Extensions | Ben Langmuir | 2013-09-17 |
* | Make F16C feature flag imply AVX rather than just checking both at the patterns. | Craig Topper | 2013-09-16 |
* | Add the remaining Intel SHA instructions | Ben Langmuir | 2013-09-14 |
* | Adds support for Atom Silvermont (SLM) - -march=slm | Preston Gurd | 2013-09-13 |
* | Partial support for Intel SHA Extensions (sha1rnds4) | Ben Langmuir | 2013-09-12 |
* | AVX-512: implemented extractelement with variable index. | Elena Demikhovsky | 2013-09-12 |
* | Add neverHasSideEffects=1 on a couple move instructions. | Craig Topper | 2013-09-08 |
* | AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS | Elena Demikhovsky | 2013-08-28 |
* | AVX-512: added conversion instructions. | Elena Demikhovsky | 2013-08-27 |
* | AVX-512: Added shuffle instructions - | Elena Demikhovsky | 2013-08-26 |
* | AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ | Elena Demikhovsky | 2013-08-20 |
* | Move AVX and non-AVX replication inside a couple multiclasses to avoid repeat... | Craig Topper | 2013-08-20 |