| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | Add instruction encodings / disassembly support for l2r instructions. | Richard Osborne | 2012-12-17 |
| * | Add instruction encodings / disassembly support for rus instructions. | Richard Osborne | 2012-12-17 |
| * | Add instruction encodings / disassembly support for 2r instructions. | Richard Osborne | 2012-12-17 |
| * | Add instruction encodings / disassembly support for 0r instructions. | Richard Osborne | 2012-12-17 |
| * | Add instruction encodings and disassembly for 1r instructions. | Richard Osborne | 2012-12-16 |
| * | Remove invalid instruction encodings. | Richard Osborne | 2012-12-16 |
| * | Mark anything deriving from PseudoInstXCore as a pseudo instruction. | Richard Osborne | 2012-12-16 |
| * | Set instruction size correctly in XCoreInstrFormats.td | Richard Osborne | 2012-12-16 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 |
| * | Add XCore backend. | Richard Osborne | 2008-11-07 |
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