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Commit message (Expand)AuthorAge
* Sometimes isPredicable lies to us and tells us we don't need the operands.Eric Christopher2011-03-12
* Add FIXME.Jim Grosbach2011-03-12
* Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the sameJim Grosbach2011-03-12
* Add a FIXME.Jim Grosbach2011-03-11
* Pseudo-ize the ARM 'B' instruction.Jim Grosbach2011-03-11
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-11
* Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach2011-03-11
* 80 columnsJim Grosbach2011-03-11
* Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-Jim Grosbach2011-03-11
* ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach2011-03-11
* ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach2011-03-11
* ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach2011-03-11
* This FIXME has been fixed.Jim Grosbach2011-03-11
* Properly pseudo-ize ARM MVNCCi.Jim Grosbach2011-03-11
* Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).Jim Grosbach2011-03-11
* silence a conditional assignment -Wuninitialized warning.Chris Lattner2011-03-11
* Properly pseudo-ize ARM MOVCCi and MOVCCi16.Jim Grosbach2011-03-11
* Change the x86 32-bit scheduler to register pressure and fix up theEric Christopher2011-03-11
* Properly pseudo-ize MOVCCr and MOVCCs.Jim Grosbach2011-03-10
* DMB can just be a pat referencing MCR.Jim Grosbach2011-03-10
* Reorganize a bit. No functional change, just moving patterns up.Jim Grosbach2011-03-10
* Pseudo-instructions are codegenonly by definition.Jim Grosbach2011-03-10
* PTX: Add preliminary support for floating-point divide and multiply-and-addJustin Holewinski2011-03-10
* ptx: add the rest of special registers of ISA version 2.0Che-Liang Chiou2011-03-10
* Revert 127359; it broke lencod.Stuart Hastings2011-03-10
* Re-commit 127368 and 127371. They are exonerated.Evan Cheng2011-03-10
* Revert 127368 and 127371 for now.Evan Cheng2011-03-09
* Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be moreEvan Cheng2011-03-09
* Fix a pasto that broke all x86_64-elf targets.Benjamin Kramer2011-03-09
* X86 byval copies no longer always_inline. <rdar://problem/8706628>Stuart Hastings2011-03-09
* LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.Johnny Chen2011-03-09
* Improve varags handling, with testcases. Patch by Sasa StankovicBruno Cardoso Lopes2011-03-09
* Add createELFObjectTargetWriter method to TargetAsmBackend, which enables con...Jan Sjödin2011-03-09
* Target/X86: Tweak va_arg for Win64 not to miss taking va_start when number of...NAKAMURA Takumi2011-03-09
* * Correct encoding for VSRI.Bill Wendling2011-03-09
* Correct the encoding for VRSRA and VSRA instructions.Bill Wendling2011-03-09
* * Fix VRSHR and VSHR to have the correct encoding for the immediate.Bill Wendling2011-03-08
* X86: Fix the (saddo/ssub x, 1) -> incl/decl selection to check the right oper...Benjamin Kramer2011-03-08
* PTX: Add intrinsic support for ntid, ctaid, and nctaid registersJustin Holewinski2011-03-08
* Turn on list-ilp scheduling by default on x86 and x86-64, fix upEric Christopher2011-03-08
* Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.Bob Wilson2011-03-08
* Fix comment typos.Bob Wilson2011-03-08
* Rename the narrow shift right immediate operands to "shr_imm*" operands. AlsoBill Wendling2011-03-07
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-07
* ARM assembler stuff is crazy: for .setfp positive values of offset correspond...Anton Korobeynikov2011-03-05
* In Thumb1 mode the constant might be materialized via the load from constpool...Anton Korobeynikov2011-03-05
* Implement frame unwinding information emission for Thumb1. Not finished yet b...Anton Korobeynikov2011-03-05
* Add unwind information emission for thumb stuffAnton Korobeynikov2011-03-05
* Handle MI flags inside Thumb2SizeReduction pass.Anton Korobeynikov2011-03-05
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-05
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