summaryrefslogtreecommitdiff
path: root/lib/Target
Commit message (Collapse)AuthorAge
* Sometimes isPredicable lies to us and tells us we don't need the operands.Eric Christopher2011-03-12
| | | | | | | | | | Go ahead and add them on when we might want to use them and let later passes remove them. Fixes rdar://9118569 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127518 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FIXME.Jim Grosbach2011-03-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127516 91177308-0d34-0410-b5e6-96231b3b80d8
* Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the sameJim Grosbach2011-03-12
| | | | | | | | actual instruction as the non-Darwin defs, but have different call-clobber semantics and so need separate patterns. They don't need to duplicate the encoding information, however. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127515 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a FIXME.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127511 91177308-0d34-0410-b5e6-96231b3b80d8
* Pseudo-ize the ARM 'B' instruction.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127510 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127509 91177308-0d34-0410-b5e6-96231b3b80d8
* Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127506 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 columnsJim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127505 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-Jim Grosbach2011-03-11
| | | | | | | | effect that we get proper instruction printing using the "pop" mnemonic for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127502 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach2011-03-11
| | | | | | as for VDUP32d and VDUP32q, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127489 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach2011-03-11
| | | | | | and VDUPLN32d, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127486 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach2011-03-11
| | | | | | as for VREV64d32 and VREV64q32, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127485 91177308-0d34-0410-b5e6-96231b3b80d8
* This FIXME has been fixed.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127483 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly pseudo-ize ARM MVNCCi.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127482 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127469 91177308-0d34-0410-b5e6-96231b3b80d8
* silence a conditional assignment -Wuninitialized warning.Chris Lattner2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127453 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly pseudo-ize ARM MOVCCi and MOVCCi16.Jim Grosbach2011-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127442 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the x86 32-bit scheduler to register pressure and fix up theEric Christopher2011-03-11
| | | | | | | | | corresponding testcases back to the previous versions. Fixes some performance regressions only seen on 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127441 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly pseudo-ize MOVCCr and MOVCCs.Jim Grosbach2011-03-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127434 91177308-0d34-0410-b5e6-96231b3b80d8
* DMB can just be a pat referencing MCR.Jim Grosbach2011-03-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127423 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorganize a bit. No functional change, just moving patterns up.Jim Grosbach2011-03-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127422 91177308-0d34-0410-b5e6-96231b3b80d8
* Pseudo-instructions are codegenonly by definition.Jim Grosbach2011-03-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127420 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Add preliminary support for floating-point divide and multiply-and-addJustin Holewinski2011-03-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127410 91177308-0d34-0410-b5e6-96231b3b80d8
* ptx: add the rest of special registers of ISA version 2.0Che-Liang Chiou2011-03-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127397 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 127359; it broke lencod.Stuart Hastings2011-03-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127382 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-commit 127368 and 127371. They are exonerated.Evan Cheng2011-03-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127380 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 127368 and 127371 for now.Evan Cheng2011-03-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127376 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be moreEvan Cheng2011-03-09
| | | | | | | | | | | | | | flexible. If it returns a register class that's different from the input, then that's the register class used for cross-register class copies. If it returns a register class that's the same as the input, then no cross- register class copies are needed (normal copies would do). If it returns null, then it's not at all possible to copy registers of the specified register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127368 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a pasto that broke all x86_64-elf targets.Benjamin Kramer2011-03-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127365 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 byval copies no longer always_inline. <rdar://problem/8706628>Stuart Hastings2011-03-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127359 91177308-0d34-0410-b5e6-96231b3b80d8
* LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.Johnny Chen2011-03-09
| | | | | | | | | | The insufficient encoding information of the combined instruction confuses the decoder wrt UQADD16. Add extra logic to recover from that. Fixed an assert reported by Sean Callanan git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127354 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve varags handling, with testcases. Patch by Sasa StankovicBruno Cardoso Lopes2011-03-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127349 91177308-0d34-0410-b5e6-96231b3b80d8
* Add createELFObjectTargetWriter method to TargetAsmBackend, which enables ↵Jan Sjödin2011-03-09
| | | | | | construction of non-standard ELFObjectWriters that can be used in MCJIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127346 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/X86: Tweak va_arg for Win64 not to miss taking va_start when number ↵NAKAMURA Takumi2011-03-09
| | | | | | of fixed args > 4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127328 91177308-0d34-0410-b5e6-96231b3b80d8
* * Correct encoding for VSRI.Bill Wendling2011-03-09
| | | | | | | * Add tests for VSRI and VSLI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127297 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct the encoding for VRSRA and VSRA instructions.Bill Wendling2011-03-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127294 91177308-0d34-0410-b5e6-96231b3b80d8
* * Fix VRSHR and VSHR to have the correct encoding for the immediate.Bill Wendling2011-03-08
| | | | | | | * Update the NEON shift instruction test to expect what 'as' produces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127293 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fix the (saddo/ssub x, 1) -> incl/decl selection to check the right ↵Benjamin Kramer2011-03-08
| | | | | | | | operand for 1. Found by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127247 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Add intrinsic support for ntid, ctaid, and nctaid registersJustin Holewinski2011-03-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127246 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn on list-ilp scheduling by default on x86 and x86-64, fix upEric Christopher2011-03-08
| | | | | | | | | | | | | | | | | | | | | | | | testcases accordingly. Some are currently xfailed and will be filed as bugs to be fixed or understood. Performance results: roughly neutral on SPEC some micro benchmarks in the llvm suite are up between 100 and 150%, only a pair of regressions that are due to be investigated john-the-ripper saw: 10% improvement in traditional DES 8% improvement in BSDI DES 59% improvement in FreeBSD MD5 67% improvement in OpenBSD Blowfish 14% improvement in LM DES Small compile time impact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127208 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.Bob Wilson2011-03-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127198 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment typos.Bob Wilson2011-03-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127197 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the narrow shift right immediate operands to "shr_imm*" operands. AlsoBill Wendling2011-03-07
| | | | | | | | | expand the testing of the narrowing shift right instructions. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembler stuff is crazy: for .setfp positive values of offset ↵Anton Korobeynikov2011-03-05
| | | | | | corresponds to "add" instruction, not to "sub" as in .pad case git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127106 91177308-0d34-0410-b5e6-96231b3b80d8
* In Thumb1 mode the constant might be materialized via the load from ↵Anton Korobeynikov2011-03-05
| | | | | | constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127105 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement frame unwinding information emission for Thumb1. Not finished yet ↵Anton Korobeynikov2011-03-05
| | | | | | because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127104 91177308-0d34-0410-b5e6-96231b3b80d8
* Add unwind information emission for thumb stuffAnton Korobeynikov2011-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127103 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle MI flags inside Thumb2SizeReduction pass.Anton Korobeynikov2011-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127102 91177308-0d34-0410-b5e6-96231b3b80d8
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-05
| | | | | | | This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-27 20:52:02 +0000