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* ARMAsmParser: Plug a leak.Benjamin Kramer2013-08-03
* Stop leaking register infos in the disassemblers.Benjamin Kramer2013-08-03
* Fix PPC64 64-bit GPR inline asm constraint matchingHal Finkel2013-08-03
* Add a missing 'return' statement.Joey Gouly2013-08-02
* [mips] Expand vector truncating stores and extending loads.Akira Hatanaka2013-08-02
* [ARMv8] Add an assembler warning for the deprecated 'setend' instruction.Joey Gouly2013-08-02
* Fixes ARM LNT bot from SLP change in O3Renato Golin2013-08-02
* [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,Akira Hatanaka2013-08-01
* Use function attributes to indicate that we don't want to realign the stack.Bill Wendling2013-08-01
* Fixed the Intel-syntax X86 disassembler to respect the (existing) option for ...Daniel Malea2013-08-01
* Fix some issues with Mips16 floating when certain intrinsics are present.Reed Kotler2013-08-01
* R600: Add 64-bit float load/store supportTom Stellard2013-08-01
* R600: Use 64-bit alignment for 64-bit kernel argumentsTom Stellard2013-08-01
* R600/SI: Custom lower i64 ZERO_EXTENDTom Stellard2013-08-01
* EVEX and compressed displacement encoding for AVX512Elena Demikhovsky2013-08-01
* [SystemZ] Reuse CC results for integer comparisons with zeroRichard Sandiford2013-08-01
* [SystemZ] Prefer comparisons with zeroRichard Sandiford2013-08-01
* Moving definition of MnemonicContainsDot field from class Instruction to clas...Vladimir Medic2013-08-01
* AArch64: add initial NEON supportTim Northover2013-08-01
* XCore target: Fix Vararg handlingRobert Lytton2013-08-01
* XCore target: Add byval handlingRobert Lytton2013-08-01
* Xcore targetRobert Lytton2013-08-01
* Fix some misc. issues with Mips16 fp stubs.Reed Kotler2013-08-01
* Add an omitted IsCall=1.Reed Kotler2013-08-01
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-31
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-31
* Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"Tom Stellard2013-07-31
* R600: Do not mergevector after a vector reg is usedVincent Lejeune2013-07-31
* R600: Avoid more than 4 literals in the same instruction group at schedulingVincent Lejeune2013-07-31
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-31
* R600: Don't mix LDS and non-LDS instructions in the same groupVincent Lejeune2013-07-31
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-07-31
* R600: Remove predicated_break instVincent Lejeune2013-07-31
* [SystemZ] Implement isLegalAddressingMode()Richard Sandiford2013-07-31
* [SystemZ] Be more careful about inverting CC masks (conditional loads)Richard Sandiford2013-07-31
* [SystemZ] Be more careful about inverting CC masksRichard Sandiford2013-07-31
* [SystemZ] Move compare-and-branch generation even laterRichard Sandiford2013-07-31
* Fixed assertion in Extract128BitVector()Elena Demikhovsky2013-07-31
* [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()Richard Sandiford2013-07-31
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-31
* [SystemZ] Add RISBLG and RISBHG instruction definitionsRichard Sandiford2013-07-31
* Increment arg_count inside the loop in printInline. Patch by Joe Matarazzo.Craig Topper2013-07-31
* Changed register names (and pointer keywords) to be lower case when using Int...Craig Topper2013-07-31
* Remove trailing whitespace and some tab characters.Craig Topper2013-07-31
* Fixed incorrect disassembly for MOV16o16a when using Intel syntax.Craig Topper2013-07-31
* [mips] Rename instruction DANDi to ANDi64.Akira Hatanaka2013-07-31
* [mips] Define instruction itineraries IIArith and IILogic.Akira Hatanaka2013-07-31
* [mips] Delete instruction format for "bal".Akira Hatanaka2013-07-30
* [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias thatAkira Hatanaka2013-07-30
* [Sparc] Rewrite MBB's live-in registers for leaf functions. Also, addVenkatraman Govindaraju2013-07-30
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