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* Rework the logic for setting the TargetName. This appears toEric Christopher2014-06-27
| | | | | | be shorter and identical in goal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211845 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove caching of the target machine in NVPTXInstrInfo andEric Christopher2014-06-27
| | | | | | update constructor accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211840 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove comment that duplicated information in the constructorEric Christopher2014-06-27
| | | | | | that it's after. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211839 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove commented out code.Eric Christopher2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211838 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove extraneous parens and extraneous const cast (and fix theEric Christopher2014-06-27
| | | | | | prototype for the function to patch what we were returning). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211837 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the subtarget dependent features from the target machine toEric Christopher2014-06-27
| | | | | | the subtarget for the MSP430 target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211836 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove uses and caches of the target machine and subtarget fromEric Christopher2014-06-27
| | | | | | | | both MSP430InstrInfo and MSP430RegisterInfo. Remove unused member variable StackAlign from MSP430RegisterInfo. Update constructors accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211835 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove caching of an unused subtarget from MSP430FrameLowering.Eric Christopher2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211830 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] AVX512: Add vbroadcasti*Adam Nemet2014-06-27
| | | | | | | | | For now I used a separate template for these sub-vector/tuple broadcasts rather than sharing the mem variants with avx512_int_broadcast_rm. <rdar://problem/17402869> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211828 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary caching of variables by MSP430TargetLowering andEric Christopher2014-06-27
| | | | | | | make the constructor more general since it only needs a target machine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211827 91177308-0d34-0410-b5e6-96231b3b80d8
* Have MSP430SelectionDAGInfo constructor take a DataLayout ratherEric Christopher2014-06-27
| | | | | | | than a target machine since it doesn't need anything past the DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211826 91177308-0d34-0410-b5e6-96231b3b80d8
* Move all of the hexagon subtarget dependent variables from the targetEric Christopher2014-06-27
| | | | | | machine to the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211824 91177308-0d34-0410-b5e6-96231b3b80d8
* Have HexagonSelectionDAGInfo take a DataLayout rather than aEric Christopher2014-06-27
| | | | | | target machine since that's all it needs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211822 91177308-0d34-0410-b5e6-96231b3b80d8
* Make HexagonISelLowering not dependent upon a HexagonTargetMachine,Eric Christopher2014-06-27
| | | | | | but a normal TargetMachine and remove a few cached uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211821 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce indentation.Eric Christopher2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211820 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary caching of the subtarget for HexagonFrameLowering and ↵Eric Christopher2014-06-27
| | | | | | remove the unused constructor argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211819 91177308-0d34-0410-b5e6-96231b3b80d8
* InstrItineraryData is already on the subtarget, no reason toEric Christopher2014-06-27
| | | | | | cache it on the target as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211818 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Introduce a string_ostream string builder facilty"Alp Toker2014-06-26
| | | | | | Temporarily back out commits r211749, r211752 and r211754. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211814 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the various Subtarget dependent members down to the subtargetEric Christopher2014-06-26
| | | | | | | | for the Sparc port. Use the same initializeSubtargetDependencies function to handle initialization similar to the other ports to handle dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211811 91177308-0d34-0410-b5e6-96231b3b80d8
* Have SparcSelectionDAGInfo take a DataLayout to initialize sinceEric Christopher2014-06-26
| | | | | | that's all it needs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211810 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the storage and use of the subtarget out of the sparc frameEric Christopher2014-06-26
| | | | | | lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211809 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove extraneous includes from the target machines.Eric Christopher2014-06-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211800 91177308-0d34-0410-b5e6-96231b3b80d8
* Move all of the ARM subtarget features down onto the subtargetEric Christopher2014-06-26
| | | | | | rather than the target machine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211799 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the frame lowering constructors out of line to avoid circularEric Christopher2014-06-26
| | | | | | includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211798 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add FP mode bits to binary.Matt Arsenault2014-06-26
| | | | | | | | The default rounding mode to initialize the mode register needs to be reported to the runtime. Fill in other bits a kernel may be interested in setting for future use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211791 91177308-0d34-0410-b5e6-96231b3b80d8
* Silencing a warning about isZExtFree hiding an inherited virtual function. ↵Aaron Ballman2014-06-26
| | | | | | No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211783 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence a warning due to a comparison between signed and unsigned.Andrea Di Biagio2014-06-26
| | | | | | | | No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211782 91177308-0d34-0410-b5e6-96231b3b80d8
* add ppc64/pwr8 as targetWill Schmidt2014-06-26
| | | | | | | | | includes handling DIR_PWR8 where appropriate The P7Model Itinerary is currently tied in for use under the P8Model, and will be updated later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211779 91177308-0d34-0410-b5e6-96231b3b80d8
* Added parsing co-processor names starting with "cr"Renato Golin2014-06-26
| | | | | | | | | | Additional compliant GAS names for coprocessor register name are enabled for all instruction with parameter MCK_CoprocReg: LDC,LDC2,STC,STC2,CDP,CDP2,MCR,MCR2,MCRR,MCRR2,MRC,MRC2,MRRC,MRRC2 Patch by Andrey Kuharev. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211776 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Improve the selection of SSE3/AVX addsub instructions. Andrea Di Biagio2014-06-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch teaches the backend how to canonicalize a shuffle vectors according to the rule: - (shuffle (FADD A, B), (FSUB A, B), Mask) -> (shuffle (FSUB A, -B), (FADD A, -B), Mask) Where 'Mask' is: <0,5,2,7> ;; for v4f32 and v4f64 shuffles. <0,3> ;; for v2f64 shuffles. <0,9,2,11,4,13,6,15> ;; for v8f32 shuffles. In general, ISel only knows how to pattern-match a canonical 'fadd + fsub + blendi' dag node sequence into an ADDSUB instruction. This new rule allows to convert a non-canonical dag sequence into a canonical one that will be matched by a single ADDSUB at ISel stage. The idea of converting a non-canonical ADDSUB into a canonical one by swapping the first two operands of the shuffle, and then negating the second operand of the FADD and FSUB, was originally proposed by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211771 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix vector FMAMatt Arsenault2014-06-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211757 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] AVX512: Fix asm syntax for packed vcmpAdam Nemet2014-06-26
| | | | | | | | The *_alt defs for vcmp are used by the InstParser (the asm string in the main def is used by the InstPrinter) . The former was accepting vector registers as destination rather than mask registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211750 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce a string_ostream string builder faciltyAlp Toker2014-06-26
| | | | | | | | | | | | | | | | | | | | string_ostream is a safe and efficient string builder that combines opaque stack storage with a built-in ostream interface. small_string_ostream<bytes> additionally permits an explicit stack storage size other than the default 128 bytes to be provided. Beyond that, storage is transferred to the heap. This convenient class can be used in most places an std::string+raw_string_ostream pair or SmallString<>+raw_svector_ostream pair would previously have been used, in order to guarantee consistent access without byte truncation. The patch also converts much of LLVM to use the new facility. These changes include several probable bug fixes for truncated output, a programming error that's no longer possible with the new interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211749 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] More refactoring of select lowering and XALU folding. NFC.Juergen Ributzka2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211740 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Refactor XALU folding. NFC.Juergen Ributzka2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211735 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Only fold the cmp into the select when both instructions are ↵Juergen Ributzka2014-06-25
| | | | | | | | | | | | in the same basic block. If the cmp is in a different basic block, then it is possible that not all operands of that compare have defined registers. This can happen when one of the operands to the cmp is a load and the load gets folded into the cmp. In this case FastISel will skip the load instruction and the vreg is never defined. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211730 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Always prefer to lower a VECTOR_SHUFFLE into a BLENDI instead of SHUFP ↵Andrea Di Biagio2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (or VPERM2X128). This patch teaches method 'LowerVECTOR_SHUFFLE' to give higher precedence to the check for 'isBlendMask'; the idea is that, when possible, we should firstly check if a shuffle performs a blend, and in case, try to lower it into a BLENDI instead of selecting a SHUFP or (worse) a VPERM2X128. In general: - AVX VBLENDPS/D always have better latency and throughput than VPERM2F128; - BLENDPS/D instructions tend to always have better 'reciprocal throughput' than the equivalent SHUFPS/D; - Both BLENDPS/D and SHUFPS/D are often decoded into the same number of m-ops; however, a m-op obtained from a BLENDPS/D can be scheduled to more than one execution port. This patch: - Moves the check for 'isBlendMask' immediately before the check for 'isSHUFPMask' within method 'LowerVECTOR_SHUFFLE'; - Updates existing tests for sse/avx shuffle/blend instructions to verify that we select (v)blendps/d when possible (instead of (v)shufps/d or vperm2f128). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211720 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix indentation.Juergen Ributzka2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211717 91177308-0d34-0410-b5e6-96231b3b80d8
* Move expression visitation logic up to MCStreamer.Rafael Espindola2014-06-25
| | | | | | Remove the duplicate from MCRecordStreamer. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211714 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify the visitation of target expressions. No functionality change.Rafael Espindola2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211707 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add intrinsics for the pshufd, pshuflw, and pshufhw instructions.Chandler Carruth2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211694 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply r211399, "Generate native unwind info on Win64" with a fix to ↵NAKAMURA Takumi2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | ignore SEH pseudo ops in X86 JIT emitter. -- This patch enables LLVM to emit Win64-native unwind info rather than DWARF CFI. It handles all corner cases (I hope), including stack realignment. Because the unwind info is not flexible enough to describe stack frames with a gap of unknown size in the middle, such as the one caused by stack realignment, I modified register spilling code to place all spills into the fixed frame slots, so that they can be accessed relative to the frame pointer. Patch by Vadim Chugunov! Reviewed By: rnk Differential Revision: http://reviews.llvm.org/D4081 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211691 91177308-0d34-0410-b5e6-96231b3b80d8
* Reformat.NAKAMURA Takumi2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211689 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add target combine rule to select ADDSUB instructions from a build_vectorAndrea Di Biagio2014-06-25
| | | | | | | | | | | | | | | | | | | This patch teaches the backend how to combine a build_vector that implements an 'addsub' between packed float vectors into a sequence of vector add and vector sub followed by a VSELECT. The new VSELECT is expected to be lowered into a BLENDI. At ISel stage, the sequence 'vector add + vector sub + BLENDI' is pattern-matched against ISel patterns added at r211427 to select 'addsub' instructions. Added three more ISel patterns for ADDSUB. Added test sse3-avx-addsub-2.ll to verify that we correctly emit 'addsub' instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211679 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Fold XALU condition into branch and compare.Juergen Ributzka2014-06-24
| | | | | | | Optimize the codegen of select and branch instructions to directly use the EFLAGS from the {s|u}{add|sub|mul}.with.overflow intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211645 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use a ComplexPattern for MUBUF storesTom Stellard2014-06-24
| | | | | | | | Now that non-leaf ComplexPatterns are allowed we can fold all the MUBUF store patterns into the instruction definition. We will also be able to reuse this new ComplexPattern for MUBUF loads and atomic operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211644 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Promote i64 stores to v2i32Tom Stellard2014-06-24
| | | | | | Now we need only one 64-bit pattern for stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211643 91177308-0d34-0410-b5e6-96231b3b80d8
* Print a=b as an assignment.Rafael Espindola2014-06-24
| | | | | | | | | | | In assembly the expression a=b is parsed as an assignment, so it should be printed as one. This remove a truly horrible hack for producing a label with "a=.". It would be used by codegen but would never be reached by the asm parser. Sorry I missed this when it was first committed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211639 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-24
| | | | | | | | | | | | | R600 was using a clamped version of rsq, but SI was not. Add a new rsq_clamped intrinsic and use them consistently. It's unclear to me from the documentation what behavior the R600 instructions have, so I assume they have the legacy behavior described by the SI documents. For R600, use RECIPSQRT_IEEE for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also has RECIPSQRT_FF, which I'm not sure how it fits in here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211637 91177308-0d34-0410-b5e6-96231b3b80d8
* [PPC64] Fix PR20071 (fctiduz generated for targets lacking that instruction)Bill Schmidt2014-06-24
| | | | | | | | | | | | | | | | | | PR20071 identifies a problem in PowerPC's fast-isel implementation for floating-point conversion to integer. The fctiduz instruction was added in Power ISA 2.06 (i.e., Power7 and later). However, this instruction is being generated regardless of which 64-bit PowerPC target is selected. The intent is for fast-isel to punt to DAG selection when this instruction is not available. This patch implements that change. For testing purposes, the existing fast-isel-conversion.ll test adds a RUN line for -mcpu=970 and tests for the expected code generation. Additionally, the existing test fast-isel-conversion-p5.ll was found to be incorrectly expecting the unavailable instruction to be generated. I've removed these test variants since we have adequate coverage in fast-isel-conversion.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211627 91177308-0d34-0410-b5e6-96231b3b80d8
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