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* Convert StringMapEntry::Create to use StringRef instead of start/end ↵Craig Topper2014-06-11
| | | | | | pointers. Simpliies all in tree call sites. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210638 91177308-0d34-0410-b5e6-96231b3b80d8
* Try to fix the msvc build.Rafael Espindola2014-06-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210636 91177308-0d34-0410-b5e6-96231b3b80d8
* Uses generic_category instead of system_category.Rafael Espindola2014-06-11
| | | | | | | Some c++ libraries (libstdc++ at least) don't seem to map to the generic category in in the system_category's default_error_condition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210635 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: add enumeration of WinEH data encodingSaleem Abdulrasool2014-06-11
| | | | | | | | | | | | | | | Most Windows platforms use auxiliary data for unwinding. This information is stored in the .pdata section. The encoding format for the data differs between architectures and Windows variants. Windows MIPS and Alpha use identical formats; Alpha64 is the same with different widths. Windows x86_64 and Itanium share the representation. All Windows CE entries are identical irrespective of the architecture. ARMv7 (Windows [NT] on ARM) has its own format. This enumeration will become the differentiator once the windows EH emission infrastructure is generalised, allowing us to emit the necessary unwinding information for Windows on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210634 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove windows_error.Rafael Espindola2014-06-11
| | | | | | | | | | MSVC doesn't seem to provide any is_error_code_enum enumeration for the windows errors. Fortunately very few places in llvm have to handle raw windows errors, so we can just construct the corresponding error_code directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210631 91177308-0d34-0410-b5e6-96231b3b80d8
* There is no posix_category in std, use generic_category.Rafael Espindola2014-06-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210630 91177308-0d34-0410-b5e6-96231b3b80d8
* Use cast instead of assert + dyn_castMatt Arsenault2014-06-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210628 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add helper functions.Matt Arsenault2014-06-11
| | | | | | | Extract these from some of my other patches, since this is the only thing really making them dependent on each other. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210627 91177308-0d34-0410-b5e6-96231b3b80d8
* CodeGen: refactor DwarfExceptionSaleem Abdulrasool2014-06-11
| | | | | | | | | | | | DwarfException served as a base class for exception handling directive emission. However, this is also used by other exception models (e.g. Win64EH). Rename this class to EHStreamer and split it out of DwarfException.h. NFC. Use the opportunity to fix up some of the documentation comments to match current LLVM style. Also rename some functions to conform better with current LLVM coding style. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210622 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove duplicate copy of InstrItineraryData from the TargetMachine,Eric Christopher2014-06-11
| | | | | | it's already on the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210619 91177308-0d34-0410-b5e6-96231b3b80d8
* Move to a private function to initialize the subtarget dependenciesEric Christopher2014-06-11
| | | | | | so that we can use initializer lists for the AArch64 Subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210616 91177308-0d34-0410-b5e6-96231b3b80d8
* Move to a private function to initialize the subtarget dependenciesEric Christopher2014-06-11
| | | | | | so that we can use initializer lists for the X86Subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210614 91177308-0d34-0410-b5e6-96231b3b80d8
* Sort includes.Eric Christopher2014-06-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210613 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Extend support for {s|u}{add|sub|mul}.with.overflow intrinsics.Juergen Ributzka2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210610 91177308-0d34-0410-b5e6-96231b3b80d8
* Use unique_ptr for X86Subtarget pointer members.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210606 91177308-0d34-0410-b5e6-96231b3b80d8
* Move AArch64TargetLowering to AArch64Subtarget.Eric Christopher2014-06-10
| | | | | | | This currently necessitates a TargetMachine for the TargetLowering constructor and TLOF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210605 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Remove support for runtime multi-threading."Zachary Turner2014-06-10
| | | | | | This reverts revision r210600. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210603 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove support for runtime multi-threading.Zachary Turner2014-06-10
| | | | | | | | | | | | | | | | | | | | | This patch removes the functions llvm_start_multithreaded() and llvm_stop_multithreaded(), and changes llvm_is_multithreaded() to return a constant value based on the value of the compile-time definition LLVM_ENABLE_THREADS. Previously, it was possible to have compile-time support for threads on, and runtime support for threads off, in which case certain mutexes were not allocated or ever acquired. Now, if the build is created with threads enabled, mutexes are always acquired. A test before/after patch of compiling a very large TU showed no noticeable performance impact of this change. Reviewers: rnk Differential Revision: http://reviews.llvm.org/D4076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210600 91177308-0d34-0410-b5e6-96231b3b80d8
* Move AArch64InstrInfo to AArch64Subtarget.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210599 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a method that was just replacing direct access to a member.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210598 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the use of TargetMachine from X86InstrInfo.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210596 91177308-0d34-0410-b5e6-96231b3b80d8
* Move X86RegisterInfo away from using the TargetMachine and onlyEric Christopher2014-06-10
| | | | | | using the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210595 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark a few functions noexcept.Rafael Espindola2014-06-10
| | | | | | This reduces the difference between std::error_code and llvm::error_code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210591 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the TargetMachine on the DAG or the MachineFunction insteadEric Christopher2014-06-10
| | | | | | of using the cached TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210589 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Emit an error when attempting to spill VGPRs v4Tom Stellard2014-06-10
| | | | | | | | | | | | | | | | | | I can't get VGPR spilling to work reliable, so for now just emit an error when the register allocator tries to spill VGPRs. v2: - Fix build v3: - Added crash fix when spilling SPGRs v4: - Use V_MOV_B32 as a dummy instruction instead of S_NOP Patch by: Darren Powell https://bugs.freedesktop.org/show_bug.cgi?id=75276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210588 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix a crash when spilling SGPRsTom Stellard2014-06-10
| | | | | | | | | | | We need to make sure only one new instruction is added when spilling otherwise the register allocator may crash. This fixes a crash in the game Antichamber. https://bugs.freedesktop.org/show_bug.cgi?id=75276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210587 91177308-0d34-0410-b5e6-96231b3b80d8
* We already have a reference to the TargetMachine, use that.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210580 91177308-0d34-0410-b5e6-96231b3b80d8
* Have isInTailCallPosition take the DAG so that we can use theEric Christopher2014-06-10
| | | | | | | version of TargetLowering/Machine from there on the way to avoiding TargetMachine in TargetLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210579 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder includes to be sorted.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210578 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Patch by Ray Donnelly to print register names instead of numbers."Reid Kleckner2014-06-10
| | | | | | | | | | | | | This reverts commit r206683. The code was confusing SEH register numbers with DWARF register numbers. The test case it was committed with was obviously incorrect. The disassembler was roundtripping '.seh_pushreg %rsi' as '.seh_pushreg %rbp', and other exciting things. Noticed by Vadim Chugunov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210574 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix error in tablegen when either operand of !if is an empty list.Matt Arsenault2014-06-10
| | | | | | !if([Something], []) would error with "No type for list". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210572 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typos.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210571 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use BCNT_INT for evergreenMatt Arsenault2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210569 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210568 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210567 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Handle fcopysignMatt Arsenault2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210564 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Handle sign_extend and zero_extend to i64 with patterns.Matt Arsenault2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210563 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a FIXME.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210559 91177308-0d34-0410-b5e6-96231b3b80d8
* Move AArch64SelectionDAGInfo down to the subtarget.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210557 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel] Collect statistics about failing intrinsic calls.Juergen Ributzka2014-06-10
| | | | | | | Add more instruction-specific statistics about failing intrinsic calls during FastISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210556 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the cached little endian variable. We can get it easily offEric Christopher2014-06-10
| | | | | | of the DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210555 91177308-0d34-0410-b5e6-96231b3b80d8
* Have AArch64SelectionDAGInfo take a DataLayout parameter ratherEric Christopher2014-06-10
| | | | | | than a TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210554 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove caching of the subtarget for AArch64SelectionDAGInfo.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210553 91177308-0d34-0410-b5e6-96231b3b80d8
* Move DataLayout onto the AArch64 subtarget.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210552 91177308-0d34-0410-b5e6-96231b3b80d8
* Test commit, wraps some lines to fit in 80 columns.Zachary Turner2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210551 91177308-0d34-0410-b5e6-96231b3b80d8
* Move AArch64FrameLowering into the subtarget.Eric Christopher2014-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210549 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the uses of AArch64TargetMachine and AArch64Subtarget fromEric Christopher2014-06-10
| | | | | | AArch64FrameLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210548 91177308-0d34-0410-b5e6-96231b3b80d8
* Do Materialize Floating Point in Mips Fast-IselReed Kotler2014-06-10
| | | | | | | | | | | | | | | | | Summary: Implement materialize of floating point literals in Mips Fast-Isel Reopened version of D3659 Test Plan: simplestorefp1.ll Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4071 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210546 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Improved target combine rules for selecting horizontal add/sub.Andrea Di Biagio2014-06-10
| | | | | | | | | | | | | | | This patch slightly changes the algorithm introduced at revision 210477 to fix a problem where the algorithm was producing incorrect code for the VEX.256 encoded versions of horizontal add/sub. For these cases, we now try to split the two 256-bit vectors into 128-bit chunks before emitting horizontal add/sub dag nodes. Added a new test case into haddsub-2.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210545 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Expand i1 SELECT_CCTom Stellard2014-06-10
| | | | | | | | il is legal for Hexagon, so I should have marked this as Expand for SELECT_CC when I removed setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in r210541. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210544 91177308-0d34-0410-b5e6-96231b3b80d8
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