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* Also expand 64-bit bitcasts.Jakob Stoklund Olesen2013-05-20
* Implement spill and fill of I64Regs.Jakob Stoklund Olesen2013-05-20
* Mark i64 SETCC as expand so it is turned into a SELECT_CC.Jakob Stoklund Olesen2013-05-20
* Replace some bit operations with simpler ones. No functionality change.Benjamin Kramer2013-05-19
* Don't use %g0 to materialize 0 directly.Jakob Stoklund Olesen2013-05-19
* Select i64 values with %icc conditions.Jakob Stoklund Olesen2013-05-19
* Remove declaration of __clear_cache for __APPLE__. <rdar://problem/13924072>Bob Wilson2013-05-19
* Add floating point selects on %xcc predicates.Jakob Stoklund Olesen2013-05-19
* Implement SPselectfcc for i64 operands.Jakob Stoklund Olesen2013-05-19
* [Sparc] Rearrange integer registers' allocation order so that register alloca...Venkatraman Govindaraju2013-05-19
* Handle i64 FrameIndex nodes in SPARC v9 mode.Jakob Stoklund Olesen2013-05-19
* AArch64: make RuntimeDyld relocations idempotentTim Northover2013-05-19
* Invalidate instruction cache when setting memory to be executable.Tim Northover2013-05-19
* isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.David Majnemer2013-05-18
* LoopVectorize: Handle single edge PHIsArnold Schwaighofer2013-05-18
* Check InlineAsm clobbers in PPCCTRLoopsHal Finkel2013-05-18
* AArch64: add CMake dependency to fix very parallel buildsTim Northover2013-05-18
* X86: Bad peephole interaction between adc, MOV32r0David Majnemer2013-05-18
* Remove duplicated commentMatt Arsenault2013-05-18
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-18
* Support unaligned load/store on more ARM targetsJF Bastien2013-05-17
* Convert obj2yaml to use yamlio.Rafael Espindola2013-05-17
* Fix the build in c++11 mode.Rafael Espindola2013-05-17
* Replace redundant codeMatt Arsenault2013-05-17
* Add missing -*- C++ -*- to headersMatt Arsenault2013-05-17
* R600: Lower int_load_input to copyFromReg instead of Register nodeVincent Lejeune2013-05-17
* R600: Use bottom up scheduling algorithmVincent Lejeune2013-05-17
* R600: Use depth first scheduling algorithmVincent Lejeune2013-05-17
* R600: Replace big texture opcode switch in scheduler by usesTC/usesVCVincent Lejeune2013-05-17
* R600: Relax some vector constraints on Dot4.Vincent Lejeune2013-05-17
* R600: Improve texture handlingVincent Lejeune2013-05-17
* R600: Rename 128 bit registers.Vincent Lejeune2013-05-17
* R600: Some factorizationVincent Lejeune2013-05-17
* R600: Factorize Fetch size limit inside AMDGPUSubTargetVincent Lejeune2013-05-17
* R600: prettier dump of clampVincent Lejeune2013-05-17
* R600: Fix encoding for R600 family GPUsTom Stellard2013-05-17
* R600: Pass MCSubtargetInfo reference to R600CodeEmitterTom Stellard2013-05-17
* [Sparc] Implements hasReservedCallFrame and hasFP.Venkatraman Govindaraju2013-05-17
* X86: Make shuffle -> shift conversion more aggressive about undefs.Benjamin Kramer2013-05-17
* LoopVectorize: Simplify code. No functionality change.Benjamin Kramer2013-05-17
* r182085 introduced a change that triggered an assertion on ARM. This is an im...David Tweed2013-05-17
* [PowerPC] Fix hi/lo encoding in old-style code emitterUlrich Weigand2013-05-17
* [PowerPC] Merge/rename PPC fixup typesUlrich Weigand2013-05-17
* [PowerPC] Fix processing of ha16/lo16 fixupsUlrich Weigand2013-05-17
* Don't cast away constness.Benjamin Kramer2013-05-17
* Minor changes to the MCJITTest unittests to use the correct API for finalizingDavid Tweed2013-05-17
* R600/SI: return undef instead of null for skipped argumentsChristian Konig2013-05-17
* [Sparc] Prevent instructions that defines or uses %o7 to be in call's delay s...Venkatraman Govindaraju2013-05-16
* Generate debug info for by-value struct args even if they are not used.Adrian Prantl2013-05-16
* [mips] Improve instruction selection for pattern (store (fp_to_sint $src), $p...Akira Hatanaka2013-05-16