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* RuntimeDyld should use the memory manager API.Jim Grosbach2011-04-06
| | | | | | | | | | | | Start teaching the runtime Dyld interface to use the memory manager API for allocating space. Rather than mapping directly into the MachO object, we extract the payload for each object and copy it into a dedicated buffer allocated via the memory manager. For now, just do Segment64, so this works on x86_64, but not yet on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128973 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r128946 (pseudoization of various instructions), and fix the extra ↵Owen Anderson2011-04-05
| | | | | | imp-def of CPSR it was adding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128965 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the virtual destructor out-of-line so we have a key function.Chandler Carruth2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128964 91177308-0d34-0410-b5e6-96231b3b80d8
* Sign errorJakob Stoklund Olesen2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128963 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't crash when a value is defined after the last split point.Jakob Stoklund Olesen2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128962 91177308-0d34-0410-b5e6-96231b3b80d8
* Permit blocks to branch directly to a landing pad.Jakob Stoklund Olesen2011-04-05
| | | | | | Treat the landing pad as a normal successor when that happens. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128961 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove extraneous 'return'.Jim Grosbach2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128959 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo in the handling of PKHTB opcode, plus add sanity check for ↵Johnny Chen2011-04-05
| | | | | | | | | | | illegal register encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up some code for clarity.Bob Wilson2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128953 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r128946 while I figure out why it broke the buildbots.Owen Anderson2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128951 91177308-0d34-0410-b5e6-96231b3b80d8
* A7.3 register encodingJohnny Chen2011-04-05
| | | | | | | | | | | | | | Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to encode function's template parameters.Devang Patel2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128947 91177308-0d34-0410-b5e6-96231b3b80d8
* Give RSBS and RSCS the pseudo treatment.Owen Anderson2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128946 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM disassembler was erroneously accepting an invalid RSC instruction.Johnny Chen2011-04-05
| | | | | | | | | Added checks for regs which should not be 15. rdar://problem/9237734 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8
* remove postdom frontiers, because it is dead. Forward dom frontiers areChris Lattner2011-04-05
| | | | | | | still used by RegionInfo :( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128943 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM disassembler was erroneously accepting an invalid LSL instruction.Johnny Chen2011-04-05
| | | | | | | | | | For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as ↵Owen Anderson2011-04-05
| | | | | | doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128940 91177308-0d34-0410-b5e6-96231b3b80d8
* Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.Jakob Stoklund Olesen2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128935 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor.Devang Patel2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128929 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an assertion instead of crashing when the scavenger goes past the endBob Wilson2011-04-05
| | | | | | of a basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128925 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typos. Adjust some whitespace for style. No functionality change.Nick Lewycky2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128924 91177308-0d34-0410-b5e6-96231b3b80d8
* The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.Johnny Chen2011-04-05
| | | | | | | | | Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change. rdar://problem/9236873 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128922 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for detection of Intel SandyBridge.Roman Divacky2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128920 91177308-0d34-0410-b5e6-96231b3b80d8
* When dead code elimination removes all but one use, try to fold the single ↵Jakob Stoklund Olesen2011-04-05
| | | | | | | | def into the remaining use. Rematerialization can leave single-use loads behind that we might as well fold whenever possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128918 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not emit empty name.Devang Patel2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128914 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.Johnny Chen2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128913 91177308-0d34-0410-b5e6-96231b3b80d8
* Added *hidden* flags -print-options and -print-all-options soAndrew Trick2011-04-05
| | | | | | | | | | | | | | | | | | | | developers can see if their driver changed any cl::Option's. The current implementation isn't perfect but handles most kinds of options. This is nice to have when decomposing the stages of compilation and moving between different drivers. It's also a good sanity check when comparing results produced by different command line invocations that are expected to produce the comparable results. Note: This is not an attempt to prolong the life of cl::Option. On the contrary, it's a placeholder for a feature that must exist when cl::Option is replaced by a more appropriate framework. A new framework needs: a central option registry, dynamic name lookup, non-global containers of option values (e.g. per-module, per-function), *and* the ability to print options values and their defaults at any point during compilation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128910 91177308-0d34-0410-b5e6-96231b3b80d8
* An MCDisassembler has the option to not implementShantonu Sen2011-04-05
| | | | | | | | | | | getEDInfo(), in which case this code would dereference NULL. EDInst can already handle NULL info, so avoid the dereference and pass NULL through. Reviewed by Sean Callanan git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128904 91177308-0d34-0410-b5e6-96231b3b80d8
* Make second source operand of LDRD pre/post explicit.Jim Grosbach2011-04-05
| | | | | | | | Finish what r128736 started. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128903 91177308-0d34-0410-b5e6-96231b3b80d8
* Constants with multiple encodings (ARM):Johnny Chen2011-04-05
| | | | | | | | | | | An alternative syntax is available for a modified immediate constant that permits the programmer to specify the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where: <byte> is the numeric value of abcdefgh, in the range 0-255 <rot> is twice the numeric value of rotation, an even number in the range 0-30. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for invalid register encodings for UMAAL and friends where:Johnny Chen2011-04-05
| | | | | | | | | | if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; if dHi == dLo then UNPREDICTABLE; rdar://problem/9230202 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128895 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert ADCS and SBCS instructions into pseudos that are expanded to the ↵Owen Anderson2011-04-05
| | | | | | ADC/ABC with the appropriate S-bit input value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128892 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure all defs referring to a virtual register are marked dead by ↵Jakob Stoklund Olesen2011-04-05
| | | | | | | | | | | | addRegisterDead(). There can be multiple defs for a single virtual register when they are defining sub-registers. The missing <dead> flag was stopping the inline spiller from eliminating dead code after rematerialization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128888 91177308-0d34-0410-b5e6-96231b3b80d8
* Print visibility info for external variables.Rafael Espindola2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128887 91177308-0d34-0410-b5e6-96231b3b80d8
* Use std::unique instead of a SmallPtrSet to ensure unique instructions in ↵Jakob Stoklund Olesen2011-04-05
| | | | | | | | | | | UseSlots. This allows us to always keep the smaller slot for an instruction which is what we want when a register has early clobber defines. Drop the UsingInstrs set and the UsingBlocks map. They are no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128886 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine optimizes gep(bitcast(x)) even when the bitcasts casts away addressNadav Rotem2011-04-05
| | | | | | | | | space info. We crash with an assert in this case. This change checks that the address space of the bitcasted pointer is the same as the gep ptr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128884 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop precomputing last split points, query the SplitAnalysis cache on demand.Jakob Stoklund Olesen2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128875 91177308-0d34-0410-b5e6-96231b3b80d8
* Cache the fairly expensive last split point computation and provide a fastJakob Stoklund Olesen2011-04-05
| | | | | | | | | inlined path for the common case. Most basic blocks don't contain a call that may throw, so the last split point os simply the first terminator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128874 91177308-0d34-0410-b5e6-96231b3b80d8
* Revamp the SjLj "dispatch setup" intrinsic.Bill Wendling2011-04-05
| | | | | | | | | | | | | It needed to be moved closer to the setjmp statement, because the code directly after the setjmp needs to know about values that are on the stack. Also, the 'bitcast' of the function context was causing a dead load. This wouldn't be too horrible, except that at -O0 it wasn't optimized out, and because it wasn't using the correct base pointer (if there is a VLA), it would try to access a value from a garbage address. <rdar://problem/9130540> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128873 91177308-0d34-0410-b5e6-96231b3b80d8
* Just use BL all the time. It's safer that way.Eric Christopher2011-04-05
| | | | | | | Fixes rdar://9184526 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128869 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 123704; it broke threaded LLVM.Stuart Hastings2011-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128868 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SRS/SRSW encoding bits.Johnny Chen2011-04-05
| | | | | | | | | | rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with http://llvm.org/viewvc/llvm-project?view=rev&revision=128859. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.105 MULJohnny Chen2011-04-04
| | | | | | | | | Inst{15-12} should be specified as 0b0000. rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128862 91177308-0d34-0410-b5e6-96231b3b80d8
* RFE encoding should also specify the "should be" encoding bits.Johnny Chen2011-04-04
| | | | | | | | | | rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while doing regression testings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128859 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing file from r128851.Jim Grosbach2011-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128856 91177308-0d34-0410-b5e6-96231b3b80d8
* Layer the memory manager between the JIT and the runtime Dyld.Jim Grosbach2011-04-04
| | | | | | | | | | | | The JITMemory manager references LLVM IR constructs directly, while the runtime Dyld works at a lower level and can handle objects which may not originate from LLVM IR. Introduce a new layer for the memory manager to handle the interface between them. For the MCJIT, this layer will be almost entirely simply a call-through w/ translation between the IR objects and symbol names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128851 91177308-0d34-0410-b5e6-96231b3b80d8
* Make OpcodeMask an unsigned long long literal to deal with overflow.Joerg Sonnenberger2011-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128847 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow coalescing with reserved physregs in certain cases:Jakob Stoklund Olesen2011-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | When a virtual register has a single value that is defined as a copy of a reserved register, permit that copy to be joined. These virtual register are usually copies of the stack pointer: %vreg75<def> = COPY %ESP; GR32:%vreg75 MOV32mr %vreg75, 1, %noreg, 0, %noreg, %vreg74<kill> MOV32mi %vreg75, 1, %noreg, 8, %noreg, 0 MOV32mi %vreg75<kill>, 1, %noreg, 4, %noreg, 0 CALLpcrel32 ... Coalescing these virtual registers early decreases register pressure. Previously, they were coalesced by RALinScan::attemptTrivialCoalescing after register allocation was completed. The lower register pressure causes the mcinst-lowering-cmp0.ll test case to fail because it depends on linear scan spilling a particular register. I am deleting 2008-08-05-SpillerBug.ll because it is counting the number of instructions emitted, and its revision history shows the 'correct' count being edited many times. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128845 91177308-0d34-0410-b5e6-96231b3b80d8
* Extract physreg joining policy to a separate method.Jakob Stoklund Olesen2011-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128844 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix incorrect alignment for NEON VST2b32_UPD.Johnny Chen2011-04-04
| | | | | | | rdar://problem/9225433 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
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