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* rip out a ton of intrinsic modernization logic from AutoUpgrade.cpp, which isChris Lattner2011-06-18
* Add an alternative rev16 pattern. We should figure out a better way to handle...Evan Cheng2011-06-17
* make the asmparser reject function and type redefinitions. 'Merging' hasn't ...Chris Lattner2011-06-17
* Remove support for using "foo" as symbols instead of %"foo". This is ancientChris Lattner2011-06-17
* manually upgrade a bunch of tests to modern syntax, and remove some thatChris Lattner2011-06-17
* Update an insertion point iterator after replacing a return instruction with aCameron Zwarich2011-06-17
* Force a triple here so this test doesn't fail on EABI hosts (like clang-nativ...Eli Friedman2011-06-16
* Typos.Chad Rosier2011-06-16
* Revision r128665 added an optimization to make use of NEON multiplierChad Rosier2011-06-16
* Testcase for previous commit.Rafael Espindola2011-06-15
* Another revsh pattern. rdar://9609059Evan Cheng2011-06-15
* PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iffEvan Cheng2011-06-15
* Add an optimization that looks for a specific pair-wise add pattern and gener...Tanya Lattner2011-06-14
* Since ARM's prefetch implementation predicted the presence of a instructionBruno Cardoso Lopes2011-06-14
* Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes2011-06-14
* Be less aggressive about hinting in RAFast.Jakob Stoklund Olesen2011-06-13
* A CCState was being created without setting whether it is in the Call or Prol...Cameron Zwarich2011-06-09
* Another possible bug. Stopgap until we can autogenerate tables andEric Christopher2011-06-03
* Fix an off by one error.Eric Christopher2011-06-03
* Make the Uv constraint a memory operand. This doesn't solve theEric Christopher2011-06-03
* Add ARM fast-isel support for materializing the address of a global in cases ...Eli Friedman2011-06-03
* During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALU...Devang Patel2011-06-02
* Allow bitcasts between valid types of the same size and vectorEric Christopher2011-06-01
* On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall2011-05-29
* I didn't mean to commit these residues of a personal project.John McCall2011-05-29
* On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall2011-05-29
* Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairsBruno Cardoso Lopes2011-05-28
* Implement the 'M' output modifier for arm inline asm. This is fairlyEric Christopher2011-05-28
* Fix the remaining atomic intrinsics to use the right register classes on Thumb2,Cameron Zwarich2011-05-27
* Make size computation less brittle.Rafael Espindola2011-05-27
* Make room for register allocation to improve.Jakob Stoklund Olesen2011-05-27
* Don't use movw / movt for iOS static codegen for now to workaround some tools...Evan Cheng2011-05-27
* Add iOS testEvan Cheng2011-05-27
* And fix the test in r132194.Eli Friedman2011-05-27
* Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076Eli Friedman2011-05-27
* During branch folding avoid inserting redundant DBG_VALUE machine instructions.Devang Patel2011-05-26
* Rewrite fast-isel integer cast handling to handle more cases, and to be simpl...Eli Friedman2011-05-25
* Implement the 'm' modifier. Note that it only works for memory operands.Eric Christopher2011-05-25
* Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. ThisCameron Zwarich2011-05-25
* Implement the arm 'L' asm modifier.Eric Christopher2011-05-24
* Implement the immediate part of the 'B' modifier.Eric Christopher2011-05-24
* Add support for the arm 'y' asm modifier.Eric Christopher2011-05-24
* Fix <rdar://problem/9476260> by having tail calls always generate 32-bit bran...Cameron Zwarich2011-05-23
* RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset ...Renato Golin2011-05-22
* Handle perfect shuffle case that generates a vrev for vectors of floats.Tanya Lattner2011-05-18
* In r131488 I misunderstood how VREV works. It splits the vector in half and s...Tanya Lattner2011-05-18
* vrev is incorrectly defined in the perfect shuffle table. The ordering is bac...Tanya Lattner2011-05-17
* Teach LiveInterval::isZeroLength about null SlotIndexes.Jakob Stoklund Olesen2011-05-16
* Correction. Use explicit target triple in the test.Galina Kistanova2011-05-12
* Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain).Nadav Rotem2011-05-11