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* rip out a ton of intrinsic modernization logic from AutoUpgrade.cpp, which isChris Lattner2011-06-18
| | | | | | | | | | | for pre-2.9 bitcode files. We keep x86 unaligned loads, movnt, crc32, and the target indep prefetch change. As usual, updating the testsuite is a PITA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133337 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an alternative rev16 pattern. We should figure out a better way to ↵Evan Cheng2011-06-17
| | | | | | handle these complex rev patterns. rdar://9609108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133289 91177308-0d34-0410-b5e6-96231b3b80d8
* make the asmparser reject function and type redefinitions. 'Merging' hasn't ↵Chris Lattner2011-06-17
| | | | | | | | | been needed since llvm-gcc 3.4 days. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133248 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove support for using "foo" as symbols instead of %"foo". This is ancientChris Lattner2011-06-17
| | | | | | | | syntax and has been long obsolete. As usual, updating the tests is the nasty part of this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133242 91177308-0d34-0410-b5e6-96231b3b80d8
* manually upgrade a bunch of tests to modern syntax, and remove some thatChris Lattner2011-06-17
| | | | | | | | are either unreduced or only test old syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133228 91177308-0d34-0410-b5e6-96231b3b80d8
* Update an insertion point iterator after replacing a return instruction with aCameron Zwarich2011-06-17
| | | | | | tail call pseudoinstruction. This fixes <rdar://problem/9624333>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133227 91177308-0d34-0410-b5e6-96231b3b80d8
* Force a triple here so this test doesn't fail on EABI hosts (like ↵Eli Friedman2011-06-16
| | | | | | clang-native-arm-cortex-a9). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133134 91177308-0d34-0410-b5e6-96231b3b80d8
* Typos.Chad Rosier2011-06-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133128 91177308-0d34-0410-b5e6-96231b3b80d8
* Revision r128665 added an optimization to make use of NEON multiplierChad Rosier2011-06-16
| | | | | | | | | | | | | | | | | | | accumulator forwarding. Specifically (from SVN log entry): Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was intended in the original revision. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133127 91177308-0d34-0410-b5e6-96231b3b80d8
* Testcase for previous commit.Rafael Espindola2011-06-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133089 91177308-0d34-0410-b5e6-96231b3b80d8
* Another revsh pattern. rdar://9609059Evan Cheng2011-06-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133064 91177308-0d34-0410-b5e6-96231b3b80d8
* PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iffEvan Cheng2011-06-15
| | | | | | | | | | | | the bits being cleared by the AND are not demanded by the BFI. The previous BFI dag combine rule was actually incorrect (or used to be correct until BFI representation changed). rdar://9609030 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133034 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an optimization that looks for a specific pair-wise add pattern and ↵Tanya Lattner2011-06-14
| | | | | | | | | generates a vpaddl instruction instead of scalarizing the add. Includes a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133027 91177308-0d34-0410-b5e6-96231b3b80d8
* Since ARM's prefetch implementation predicted the presence of a instructionBruno Cardoso Lopes2011-06-14
| | | | | | | cache prefetch and now that the info from "prefetch" to "ARMPreload" is present, only add a testcase for PLI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132978 91177308-0d34-0410-b5e6-96231b3b80d8
* Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes2011-06-14
| | | | | | | or instruction cache access. Update the targets to match it and also teach autoupgrade. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
* Be less aggressive about hinting in RAFast.Jakob Stoklund Olesen2011-06-13
| | | | | | | | | | In particular, don't spill dirty registers only to satisfy a hint. It is not worth it. The attached test case provides an example where the fast allocator would spill a register when other registers are available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132900 91177308-0d34-0410-b5e6-96231b3b80d8
* A CCState was being created without setting whether it is in the Call or ↵Cameron Zwarich2011-06-09
| | | | | | | | | | | Prologue state, causing an assertion failure downstream. This fixes <rdar://problem/9562908>. This really seems like it should always be set at CCState creation time, so mistakes like this can never happen. I'll take a look at doing that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132811 91177308-0d34-0410-b5e6-96231b3b80d8
* Another possible bug. Stopgap until we can autogenerate tables andEric Christopher2011-06-03
| | | | | | | | | | constraint lengths. Part of rdar://9037836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132598 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an off by one error.Eric Christopher2011-06-03
| | | | | | | Part of rdar://9037836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132590 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the Uv constraint a memory operand. This doesn't solve theEric Christopher2011-06-03
| | | | | | | | | addressing mode problem mentioned in r132559. Backend part of rdar://9037836 and part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132561 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM fast-isel support for materializing the address of a global in cases ↵Eli Friedman2011-06-03
| | | | | | | | | | where the global uses an indirect symbol. rdar://9431157 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132522 91177308-0d34-0410-b5e6-96231b3b80d8
* During post RA scheduling, do not try to chase reg defs. to preserve ↵Devang Patel2011-06-02
| | | | | | | | | DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132483 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow bitcasts between valid types of the same size and vectorEric Christopher2011-06-01
| | | | | | | | | types if the vector type is legal. Fixes rdar://9306086 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132420 91177308-0d34-0410-b5e6-96231b3b80d8
* On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall2011-05-29
| | | | | | | | | | | This is important for the correct lowering of unwind instructions (which doesn't matter at all) and llvm.eh.resume calls (which does). Take 2, now with more basic competence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132295 91177308-0d34-0410-b5e6-96231b3b80d8
* I didn't mean to commit these residues of a personal project.John McCall2011-05-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132293 91177308-0d34-0410-b5e6-96231b3b80d8
* On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall2011-05-29
| | | | | | | | | This is important for the correct lowering of unwind instructions (which doesn't matter at all) and llvm.eh.resume calls (which does). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132291 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairsBruno Cardoso Lopes2011-05-28
| | | | | | | | to load/store i64 values. Since there's no current support to explicitly declare such restrictions, implement it by using specific hardcoded register pairs during isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the 'M' output modifier for arm inline asm. This is fairlyEric Christopher2011-05-28
| | | | | | | | | | register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132242 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the remaining atomic intrinsics to use the right register classes on Thumb2,Cameron Zwarich2011-05-27
| | | | | | and add some basic tests for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
* Make size computation less brittle.Rafael Espindola2011-05-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132222 91177308-0d34-0410-b5e6-96231b3b80d8
* Make room for register allocation to improve.Jakob Stoklund Olesen2011-05-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132213 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use movw / movt for iOS static codegen for now to workaround some ↵Evan Cheng2011-05-27
| | | | | | tools issues. rdar://9514789 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132211 91177308-0d34-0410-b5e6-96231b3b80d8
* Add iOS testEvan Cheng2011-05-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132203 91177308-0d34-0410-b5e6-96231b3b80d8
* And fix the test in r132194.Eli Friedman2011-05-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132196 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076Eli Friedman2011-05-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132194 91177308-0d34-0410-b5e6-96231b3b80d8
* During branch folding avoid inserting redundant DBG_VALUE machine instructions.Devang Patel2011-05-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132148 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite fast-isel integer cast handling to handle more cases, and to be ↵Eli Friedman2011-05-25
| | | | | | | | | | | | simpler and more consistent. The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts). rdar://9437928 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132099 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the 'm' modifier. Note that it only works for memory operands.Eric Christopher2011-05-25
| | | | | | | Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132081 91177308-0d34-0410-b5e6-96231b3b80d8
* Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. ThisCameron Zwarich2011-05-25
| | | | | | fixes <rdar://problem/9495913> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132042 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the arm 'L' asm modifier.Eric Christopher2011-05-24
| | | | | | | Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132024 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the immediate part of the 'B' modifier.Eric Christopher2011-05-24
| | | | | | | Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132023 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the arm 'y' asm modifier.Eric Christopher2011-05-24
| | | | | | | Fixes part of rdar://9444657 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132011 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix <rdar://problem/9476260> by having tail calls always generate 32-bit ↵Cameron Zwarich2011-05-23
| | | | | | | | branches in Darwin Thumb2 code. Tail calls are already disabled on Thumb1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131894 91177308-0d34-0410-b5e6-96231b3b80d8
* RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset ↵Renato Golin2011-05-22
| | | | | | accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131868 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle perfect shuffle case that generates a vrev for vectors of floats.Tanya Lattner2011-05-18
| | | | | | | Add test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
* In r131488 I misunderstood how VREV works. It splits the vector in half and ↵Tanya Lattner2011-05-18
| | | | | | | | | splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. Updated test case and reverted change to the PerfectShuffle Table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
* vrev is incorrectly defined in the perfect shuffle table. The ordering is ↵Tanya Lattner2011-05-17
| | | | | | backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131488 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach LiveInterval::isZeroLength about null SlotIndexes.Jakob Stoklund Olesen2011-05-16
| | | | | | | | | | | | When instructions are deleted, they leave tombstone SlotIndex entries. The isZeroLength method should ignore these null indexes. This causes RABasic to sometimes spill a callee-saved register in the abi-isel.ll test, so don't run that test with -regalloc=basic. Prioritizing register allocation according to spill weight can cause more registers to be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131436 91177308-0d34-0410-b5e6-96231b3b80d8
* Correction. Use explicit target triple in the test.Galina Kistanova2011-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131252 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain).Nadav Rotem2011-05-11
| | | | | | | | | | If there is a store after the load node, then there is a chain, which means that there is another user. Thus, asking hasOneUser would fail. Instead we ask hasNUsesOfValue on the 'data' value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131183 91177308-0d34-0410-b5e6-96231b3b80d8
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