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* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-04
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-04
* Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng2013-06-04
* ARM: Fix crash in ARM backend inside of ARMConstantIslandPassDavid Majnemer2013-06-04
* R600: Swizzle texture/export instructionsVincent Lejeune2013-06-04
* R600: Add a test for r183108Vincent Lejeune2013-06-04
* R600/SI: Add support for work item and work group intrinsicsTom Stellard2013-06-03
* R600/SI: Add a calling convention for compute shadersTom Stellard2013-06-03
* R600/SI: Custom lower i64 sign_extendTom Stellard2013-06-03
* R600/SI: Add support for global loadsTom Stellard2013-06-03
* R600: use capital letter for PV channelVincent Lejeune2013-06-03
* Sparc: Add support for indirect branch and blockaddress in Sparc backend.Venkatraman Govindaraju2013-06-03
* Sparc: When storing 0, use %g0 directly in the store instruction instead ofVenkatraman Govindaraju2013-06-03
* Sparc: Combine add/or/sethi instruction with restore if possible.Venkatraman Govindaraju2013-06-02
* Sparc: Perform leaf procedure optimization by defaultVenkatraman Govindaraju2013-06-02
* Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ...Venkatraman Govindaraju2013-06-01
* Revert r183069: "TMP: LEA64_32r fixing"Tim Northover2013-06-01
* TMP: LEA64_32r fixingTim Northover2013-06-01
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-06-01
* [Sparc] Generate correct code for leaf functions with stack objects Venkatraman Govindaraju2013-06-01
* Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as itEric Christopher2013-05-31
* Modify how the formulae are rated in Loop Strength Reduce.Quentin Colombet2013-05-31
* [SystemZ] Don't use LOAD and STORE REVERSED for volatile accessesRichard Sandiford2013-05-31
* [NVPTX] Re-enable support for virtual registers in the final outputJustin Holewinski2013-05-31
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-05-31
* [mips] Big-endian code generation for atomic instructions.Akira Hatanaka2013-05-31
* Revert r182937 and r182877.Rafael Espindola2013-05-30
* Force a triple so we don't get bitten by windows' different regalloc.Benjamin Kramer2013-05-30
* Force fragile test to the atom scheduler model.Benjamin Kramer2013-05-30
* X86: allow registers 8-15 in testTim Northover2013-05-30
* X86: use sub-register sequences for MOV*r0 operationsTim Northover2013-05-30
* [NVPTX] Fix case where a sext load of an i1 type may produce anJustin Holewinski2013-05-30
* [SystemZ] Enable unaligned accessesRichard Sandiford2013-05-30
* Change how we iterate over relocations on ELF.Rafael Espindola2013-05-30
* This testcase tests command line attributes which we don't yet support.Bill Wendling2013-05-30
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-29
* Enable FastISel on ARM for Linux and NaClJF Bastien2013-05-29
* Teach ReMaterialization to be more cunning about subregistersTim Northover2013-05-29
* [SystemZ] Two tests missing from previous commitRichard Sandiford2013-05-29
* [SystemZ] Immediate compare-and-branch supportRichard Sandiford2013-05-29
* [Sparc] Add support for leaf functions in sparc backend. Venkatraman Govindaraju2013-05-29
* [SystemZ] Register compare-and-branch supportRichard Sandiford2013-05-28
* Convert sqrt functions into sqrt instructions when -ffast-math is in effect.Preston Gurd2013-05-27
* Add a cpu to try to bring back the atom bots.Rafael Espindola2013-05-27
* Prefer to duplicate PPC Altivec loads when expanding unaligned loadsHal Finkel2013-05-26
* Fix PR16143: Insert DEBUG_VALUE before terminator.Andrew Trick2013-05-26
* PPC: Combine duplicate (offset) lvsl Altivec intrinsicsHal Finkel2013-05-25
* Track IR ordering of SelectionDAG nodes 4/4.Andrew Trick2013-05-25
* Track IR ordering of SelectionDAG nodes 3/4.Andrew Trick2013-05-25
* PPC: Initial support for permutation-based unaligned Altivec loadsHal Finkel2013-05-24