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* Fix PPC64 64-bit GPR inline asm constraint matchingHal Finkel2013-08-03
* [mips] Expand vector truncating stores and extending loads.Akira Hatanaka2013-08-02
* Temporarily revert "Debug Info Finder|Verifier: handle DbgLoc attached toEric Christopher2013-08-02
* Use function attributes to indicate that we don't want to realign the stack.Bill Wendling2013-08-01
* Fix some issues with Mips16 floating when certain intrinsics are present.Reed Kotler2013-08-01
* Debug Info Finder|Verifier: handle DbgLoc attached to instructions.Manman Ren2013-08-01
* R600: Add 64-bit float load/store supportTom Stellard2013-08-01
* R600: Use 64-bit alignment for 64-bit kernel argumentsTom Stellard2013-08-01
* R600/SI: Custom lower i64 ZERO_EXTENDTom Stellard2013-08-01
* [SystemZ] Reuse CC results for integer comparisons with zeroRichard Sandiford2013-08-01
* [SystemZ] Prefer comparisons with zeroRichard Sandiford2013-08-01
* AArch64: add initial NEON supportTim Northover2013-08-01
* XCore target: Fix Vararg handlingRobert Lytton2013-08-01
* XCore target: Add byval handlingRobert Lytton2013-08-01
* Xcore targetRobert Lytton2013-08-01
* Fix some misc. issues with Mips16 fp stubs.Reed Kotler2013-08-01
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-31
* R600: Avoid more than 4 literals in the same instruction group at schedulingVincent Lejeune2013-07-31
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-31
* [SystemZ] Implement isLegalAddressingMode()Richard Sandiford2013-07-31
* [SystemZ] Be more careful about inverting CC masks (conditional loads)Richard Sandiford2013-07-31
* [SystemZ] Be more careful about inverting CC masksRichard Sandiford2013-07-31
* [SystemZ] Move compare-and-branch generation even laterRichard Sandiford2013-07-31
* [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()Richard Sandiford2013-07-31
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-31
* Changed register names (and pointer keywords) to be lower case when using Int...Craig Topper2013-07-31
* This test may have been sensitive to the ARM ABI...Andrew Trick2013-07-30
* MI Sched fix: assert "Disconnected LRG within the scheduling region."Andrew Trick2013-07-30
* R600/SI: Expand vector fp <-> int conversionsTom Stellard2013-07-30
* [ARM] check bitwidth in PerformORCombineSaleem Abdulrasool2013-07-30
* [R600] Replicate old DAGCombiner behavior in target specific DAG combine.Quentin Colombet2013-07-30
* [DAGCombiner] insert_vector_elt: Avoid building a vector twice.Quentin Colombet2013-07-30
* Debug Info: enable verifier for testing cases.Manman Ren2013-07-29
* Debug Info: update testing cases to pass verifier.Manman Ren2013-07-29
* Proper va_arg/va_copy lowering on win64Nico Rieck2013-07-29
* Allow generation of vmla.f32 instructions when targeting Cortex-A15. The patc...Silviu Baranga2013-07-29
* Debug Info Verifier: verify SPs in llvm.dbg.sp.Manman Ren2013-07-27
* next batch of -disable-debug-info-verifierRafael Espindola2013-07-26
* [mips] Implement llvm.trap intrinsic.Akira Hatanaka2013-07-26
* Debug Info Verifier: enable verification of DICompileUnit.Manman Ren2013-07-26
* [mips] Print instructions "beq", "bne" and "or" using assembler pseudoAkira Hatanaka2013-07-26
* Add a target legalize hook for SplitVectorOperand (again)Justin Holewinski2013-07-26
* Revert "Add a target legalize hook for SplitVectorOperand"Rafael Espindola2013-07-26
* Add a target legalize hook for SplitVectorOperandJustin Holewinski2013-07-26
* PPC32 va_list is an actual structure so va_copy needs to copy the wholeRoman Divacky2013-07-25
* Debug Info: improve the verifier to check field types.Manman Ren2013-07-25
* Remove the mblaze backend from llvm.Rafael Espindola2013-07-25
* Evict local live ranges if they can be reassigned.Andrew Trick2013-07-25
* Allocate local registers in order for optimal coloring.Andrew Trick2013-07-25
* Current batch of -disable-debug-info-verifier.Rafael Espindola2013-07-25
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