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* Reenable, improve, and add MI-Sched unit tests.Andrew Trick2013-06-17
* R600: PV stores Reg id, not indexVincent Lejeune2013-06-17
* R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.Vincent Lejeune2013-06-17
* Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.Benjamin Kramer2013-06-17
* Debug Info: Simplify Frame Index handling in DBG_VALUE Machine InstructionsDavid Blaikie2013-06-16
* DebugInfo: follow up to 184045 to constrain the tests further to ensure they ...David Blaikie2013-06-15
* DebugInfo: print DBG_VALUE MachineInstrs with [] for deref and drop the offse...David Blaikie2013-06-15
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-15
* Debug Info: Don't print the display name and colon prefix for DEBUG_VALUE com...David Blaikie2013-06-15
* R600: Add SI load support for v[24]i32 and store for v2i32Tom Stellard2013-06-15
* R600: Use correct encoding for Vertex Fetch instructions on CaymanTom Stellard2013-06-14
* R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on CaymanTom Stellard2013-06-14
* Mark rematerialized super/sub registers as dead.Tim Northover2013-06-14
* SelectionDAG: Fix incorrect condition checks in some cases of folding FADD/FM...Stephen Lin2013-06-14
* Make PrologEpilogInserter save/restore all callee saved registersDerek Schuff2013-06-14
* X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX equ...Benjamin Kramer2013-06-14
* Enable FastISel on ARM for Linux and NaCl, not MCJITJF Bastien2013-06-14
* [PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.Bill Schmidt2013-06-13
* [mips] Add an IR transformation pass that optimizes calls to sqrt.Akira Hatanaka2013-06-11
* X86: Stop LEA64_32r doing unspeakable things to its arguments.Tim Northover2013-06-10
* [NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore...Justin Holewinski2013-06-10
* Add test for ARM FastISel load/store register classesJF Bastien2013-06-10
* Fix a regression I introduced when I expanded the complex pseudos inReed Kotler2013-06-09
* Refine the ARM EHABI test cases.Logan Chien2013-06-09
* Fix ARM unwind opcode assembler in several cases.Logan Chien2013-06-09
* Removed PackedDouble domain from scalar instructions. Added more formats for ...Elena Demikhovsky2013-06-09
* [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc bac...Venkatraman Govindaraju2013-06-08
* Reapply r183552. This time, use a standard type for the option to avoid templateQuentin Colombet2013-06-08
* R600: Anti dep better handled in tex clauseVincent Lejeune2013-06-07
* Add missing zextloadi1 to i64 patterns. PR16721.Jakob Stoklund Olesen2013-06-07
* Disallow i64 div/rem in PPC32 counter loopsHal Finkel2013-06-07
* Revert commits related to stack warning.Quentin Colombet2013-06-07
* Explicit triple in warn stack size test cases to not depend on OS.Quentin Colombet2013-06-07
* R600: Fix calculation of stack offset in AMDGPUFrameLoweringTom Stellard2013-06-07
* R600: Fix the fetch limits for R600 generation GPUsTom Stellard2013-06-07
* Add a backend option to warn on a given stack size limit.Quentin Colombet2013-06-07
* ARM FastISel integer sext/zext improvementsJF Bastien2013-06-07
* Teach AsmPrinter how to print odd constants.Quentin Colombet2013-06-07
* Fix a typo in asm string of BP* family of instructions. With this fixRoman Divacky2013-06-07
* Support OpenBSD's native frame protection conventions.Rafael Espindola2013-06-07
* [Sparc]: Use cmp instruction instead of subcc to compare integers.Venkatraman Govindaraju2013-06-07
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-05
* R600: Schedule copy from phys register at beginning of blockVincent Lejeune2013-06-05
* [mips] brcond + setgt/setugt instruction selection patterns.Akira Hatanaka2013-06-05
* [PATCH] Fix VGATHER* operand constraintsMichael Liao2013-06-05
* R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard2013-06-05
* Revert "R600: Add a pass that merge Vector Register"Rafael Espindola2013-06-05
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-04
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-04
* Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng2013-06-04
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