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* This reverts r155000.Joey Gouly2013-06-20
| | | | | | | | | | The cdp2 instruction should have the same restrictions as cdp on the co-processor registers. VFP instructions on v8/AArch32 share the same encoding space as cdp2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184445 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add optional datatype suffix to NEON mvn asm syntax.Jim Grosbach2013-06-18
| | | | | | rdar://14194152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184244 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the arm assembler to support this from the v7c spec:Kevin Enderby2013-06-18
| | | | | | | | | | | | | | | | "When assembling to the ARM instruction set, the .N qualifier produces an assembler error and the .W qualifier has no effect." In the pre-matcher handler in the asm parser the ".w" (wide) qualifier when in ARM mode is now discarded. And an error message is now produced when the ".n" (narrow) qualifier is used in ARM mode. Test cases for these were added. rdar://14064574 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184224 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix literal load with positive offset encodingAmaury de la Vieuville2013-06-18
| | | | | | | | | | | | When using a positive offset, literal loads where encoded as if it was negative, because: - The sign bit was not assigned to an operand - The addrmode_imm12 operand was not encoding the sign bit correctly This patch also makes the assembler look at the .w/.n specifier for loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix t2am_imm8_offset operand printing for imm=#-0Amaury de la Vieuville2013-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183913 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework r183728, suppress assert(0) for now. Its behavior depends on ↵NAKAMURA Takumi2013-06-11
| | | | | | | | assertions on win32 hosts. FIXME: Introduce yet another checker but assert(0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183736 91177308-0d34-0410-b5e6-96231b3b80d8
* It adds support for negative zero offsets for loads and stores.Mihai Popa2013-06-11
| | | | | | | Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value. Behavior already present for Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183734 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These ↵Mihai Popa2013-06-11
| | | | | | are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183733 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak a couple of tests on win32 hosts with +Asserts.NAKAMURA Takumi2013-06-11
| | | | | | | | | - Don't use assert(0), or tests may pass or fail according to assertions. - For now, The tests are marked as XFAIL for win32 hosts. FIXME: Could we avoid XFAIL to specify triple in the RUN lines? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183728 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.Tim Northover2013-06-10
| | | | | | | | | | | Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some only support Thumb mode (M-class ones currently). This makes sure such CPUs default to the correct mode and makes the AsmParser diagnose an attempt to switch modes incorrectly. rdar://14024354 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183710 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-10
| | | | | | ISB should only accepts full system sync, other options are reserved git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM unwind opcode assembler in several cases.Logan Chien2013-06-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes to ARM unwind opcode assembler: * Fix multiple .save or .vsave directives. Besides, the order is preserved now. * For the directives which will generate multiple opcodes, such as ".save {r0-r11}", the order of the unwind opcode is fixed now, i.e. the registers with less encoding value are popped first. * Fix the $sp offset calculation. Now, we can use the .setfp, .pad, .save, and .vsave directives at any order. Changes to test cases: * Add test cases to check the order of multiple opcodes for the .save directive. * Fix the incorrect $sp offset in the test case. The stack pointer offset specified in the test case was incorrect. (Changed test cases: ehabi-mc-section.ll and ehabi-mc.ll) * The opcode to restore $sp are slightly reordered. The behavior are not changed, and the new output is same as the output of GNU as. (Changed test cases: eh-directive-pad.s and eh-directive-setfp.s) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183627 91177308-0d34-0410-b5e6-96231b3b80d8
* This is a simple patch that changes RRX and RRXS to accept all registers as ↵Mihai Popa2013-06-05
| | | | | | | | operands. According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: permit upper-case BE/LE on setend instructionTim Northover2013-05-31
| | | | | | Patch by Amaury de la Vieuville. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183012 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-31
| | | | | | | | | These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183011 91177308-0d34-0410-b5e6-96231b3b80d8
* Change how we iterate over relocations on ELF.Rafael Espindola2013-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | For COFF and MachO, sections semantically have relocations that apply to them. That is not the case on ELF. In relocatable objects (.o), a section with relocations in ELF has offsets to another section where the relocations should be applied. In dynamic objects and executables, relocations don't have an offset, they have a virtual address. The section sh_info may or may not point to another section, but that is not actually used for resolving the relocations. This patch exposes that in the ObjectFile API. It has the following advantages: * Most (all?) clients can handle this more efficiently. They will normally walk all relocations, so doing an effort to iterate in a particular order doesn't save time. * llvm-readobj now prints relocations in the same way the native readelf does. * probably most important, relocations that don't point to any section are now visible. This is the case of relocations in the rela.dyn section. See the updated relocation-executable.test for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182908 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM FastISel tests, as a first step to enabling ARM FastISelDerek Schuff2013-05-14
| | | | | | | | | | | | | | | | | | | | | ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181801 91177308-0d34-0410-b5e6-96231b3b80d8
* The purpose of the patch is to fix the syntax of ARM mrc and mrc2 ↵Mihai Popa2013-05-13
| | | | | | instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AsmParser for ARM unwind directives.Logan Chien2013-05-10
| | | | | | | | | | | | | | | | | | | | This commit implements the AsmParser for fnstart, fnend, cantunwind, personality, handlerdata, pad, setfp, save, and vsave directives. This commit fixes some minor issue in the ARMELFStreamer: * The switch back to corresponding section after the .fnend directive. * Emit the unwind opcode while processing .fnend directive if there is no .handlerdata directive. * Emit the unwind opcode to .ARM.extab while processing .handlerdata even if .personality directive does not exist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181603 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch fixes two tests marked as XFAIL among the ARM assembler tests.Mihai Popa2013-05-08
| | | | | | The reference encoding is correct, but written in the wrong byte order (these are Thumb tests, while the reference is in ARM byte order). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181420 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet2013-04-26
| | | | | | | | | | | | | | | | "hint" space for Thumb actually overlaps the encoding space of the CPS instruction. In actuality, hints can be defined as CPS instructions where imod and M bits are all nil. Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe, sev) in DecodeT2CPSInstruction. This commit adds a proper diagnostic message for Imm0_4 and updates all tests. Patch by Mihail Popa <Mihail.Popa@arm.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix treatment of ARM unallocated hint instructions.Quentin Colombet2013-04-17
| | | | | | | | | | | | | | | | The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction: 1. nop (imm == 0) 2. yield (imm == 1) 3. wfe (imm == 2) 4. wfi (imm == 3) 5. sev (imm == 4) Therefore, restrict the permitted values for the "hint" instruction to 0 through 4. Patch by Mihail Popa <Mihail.Popa@arm.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179707 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add VACLT and VACLE assembly aliases.Jim Grosbach2013-04-15
| | | | | | | | | These are aliases for VACGT and VACGE, respectively, with the source operands reversed. rdar://13638090 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179575 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Correct printing of pre-indexed operands.Quentin Colombet2013-04-12
| | | | | | | | | | | | | | According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179398 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace coff-/elf-dump with llvm-readobjNico Rieck2013-04-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179361 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover2013-04-10
| | | | | | | | | | | | These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr13145 - Naming a function like a register name confuses the asm parser.Chad Rosier2013-03-19
| | | | | | | Patch by Stepan Dyatkovskiy <stpworld@narod.ru> rdar://13457826 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177463 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: permit full range of valid ADR immediates.Tim Northover2013-02-27
| | | | | | | | | This fixes an issue where trying to assemlbe valid ADR instructions would cause LLVM to hit a failed assertion. Patch by Keith Walker. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176189 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Convenience aliases for 'srs*' instructions.Jim Grosbach2013-02-23
| | | | | | | | Handle an implied 'sp' operand. rdar://11466783 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175940 91177308-0d34-0410-b5e6-96231b3b80d8
* Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵Kristof Beyls2013-02-22
| | | | | | | | | | | instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
* If bundle alignment is enabled, do not add data to a fragment with instructionsDerek Schuff2013-02-15
| | | | | | | | | | | | With bundle alignment, instructions all get their own MCFragments (unless they are in a bundle-locked group). For instructions with fixups, this is an MCDataFragment. Emitting actual data (e.g. for .long) attempts to re-use MCDataFragments, which we don't want int this case since it leads to fragments which exceed the bundle size. So, don't reuse them in this case. Also adds a test and fixes some formatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175316 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM NEON vector compare instructions take three arguments. However, the Joel Jones2013-02-14
| | | | | | | | | | | | | | | assembler should also accept a two arg form, as the docuemntation specifies that the first (destination) register is optional. This patch uses TwoOperandAliasConstraint to add the two argument form. It also fixes an 80-column formatting problem in: test/MC/ARM/neon-bitwise-encoding <rdar://problem/12909419> Clang rejects ARM NEON assembly instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175221 91177308-0d34-0410-b5e6-96231b3b80d8
* Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls2013-02-14
| | | | | | | | | | | The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-30
| | | | | | | | | | More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements runtime ARM specificJack Carter2013-01-30
| | | | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173885 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch reworks how llvm targets set Jack Carter2013-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | and update ELF header e_flags. Currently gathering information such as symbol, section and data is done by collecting it in an MCAssembler object. From MCAssembler and MCAsmLayout objects ELFObjectWriter::WriteObject() forms and streams out the ELF object file. This patch just adds a few members to the MCAssember class to store and access the e_flag settings. It allows for runtime additions to the e_flag by assembler directives. The standalone assembler can get to MCAssembler from getParser().getStreamer().getAssembler(). This patch is the generic infrastructure and will be followed by patches for ARM and Mips for their target specific use. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173882 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some additional tests for the .bundle_lock align_to_end feature that didn'tEli Bendersky2013-01-07
| | | | | | | | | | | make into the last commit. Also, update the test-generation script to generate an exhaustive test for align_to_end as well, and include the generated test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171811 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the align_to_end option to .bundle_lock in the MC implementation of alignedEli Bendersky2013-01-07
| | | | | | | | | | bundling. The document describing this feature and the implementation has also been updated: https://sites.google.com/a/chromium.org/dev/nativeclient/pnacl/aligned-bundling-support-in-llvm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171797 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests for the aligned bundling support added in r170718Eli Bendersky2012-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170719 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure the alternate PC+imm syntax of LDR instruction with a smallKevin Enderby2012-12-14
| | | | | | | | | immediate generates the narrow version. Needed when doing round-trip assemble/disassemble testing using the alternate syntax that specifies 'pc' directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170255 91177308-0d34-0410-b5e6-96231b3b80d8
* revert the test changeHao Liu2012-12-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169823 91177308-0d34-0410-b5e6-96231b3b80d8
* A newbie try a test commitHao Liu2012-12-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169821 91177308-0d34-0410-b5e6-96231b3b80d8
* Added Mapping Symbols for ARM ELFTim Northover2012-12-07
| | | | | | | | | | Before this patch, when you objdump an LLVM-compiled file, objdump tried to decode data-in-code sections as if they were code. This patch adds the missing Mapping Symbols, as defined by "ELF for the ARM Architecture" (ARM IHI 0044D). Patch based on work by Greg Fitzgerald. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169609 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert an improper CodeGen test to a MC test.Evan Cheng2012-11-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167663 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-30
| | | | | | | | | When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166991 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-29
| | | | | | | | is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r165480.Craig Topper2012-10-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165594 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.Jim Grosbach2012-09-25
| | | | | | rdar://9795790 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164577 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix edge cases of ARM shift operands in arith instructions.Tim Northover2012-09-22
| | | | | | | | | As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164456 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the handling of edge cases in ARM shifted operands.Tim Northover2012-09-22
| | | | | | | | | This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
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