summaryrefslogtreecommitdiff
path: root/test/MC
Commit message (Collapse)AuthorAge
* Added parsing co-processor names starting with "cr"Renato Golin2014-06-26
| | | | | | | | | | Additional compliant GAS names for coprocessor register name are enabled for all instruction with parameter MCK_CoprocReg: LDC,LDC2,STC,STC2,CDP,CDP2,MCR,MCR2,MCRR,MCRR2,MRC,MRC2,MRRC,MRRC2 Patch by Andrey Kuharev. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211776 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] AVX512: Fix asm syntax for packed vcmpAdam Nemet2014-06-26
| | | | | | | | The *_alt defs for vcmp are used by the InstParser (the asm string in the main def is used by the InstPrinter) . The former was accepting vector registers as destination rather than mask registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211750 91177308-0d34-0410-b5e6-96231b3b80d8
* ldr-pseudo-obj-errors.s: Fix silly copypasto.NAKAMURA Takumi2014-06-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211642 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/MC/AArch64/ldr-pseudo-obj-errors.s: Add -triple=aarch64-linux. ↵NAKAMURA Takumi2014-06-24
| | | | | | | | AArch64 is unaware of PECOFF for now. FIXME: This should pass for also targeting aarch64-darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211640 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test case in r211605/r211533Weiming Zhao2014-06-24
| | | | | | | | | The test case in "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" should only work with Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211613 91177308-0d34-0410-b5e6-96231b3b80d8
* Resubmit commit r211533Weiming Zhao2014-06-24
| | | | | | | | | "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" Missed files are added in this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211605 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Added support for assembling sdbbp.Daniel Sanders2014-06-24
| | | | | | | | | | | Summary: This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too. Differential Revision: http://reviews.llvm.org/D4265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211590 91177308-0d34-0410-b5e6-96231b3b80d8
* [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fieldsAdam Nemet2014-06-24
| | | | | | | | | V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and NDS register fields. This was simply not used in the decoder until now. Fixes <rdar://problem/17402661> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211565 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the default input for llvm-nm to be a.out instead of standard inputKevin Enderby2014-06-23
| | | | | | | | | | to match llvm-size and other UNIX systems for their nm(1). Tweak test cases that used llvm-nm with standard input to add a "-" to indicate that and add a test case to check the default of a.out for llvm-nm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211529 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow using .cfi_startproc without a leading symbol.Rafael Espindola2014-06-23
| | | | | | This is possible now that we don't produce .eh symbols. This fixes pr19430. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211502 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop producing func.eh symbols on Darwin.Rafael Espindola2014-06-23
| | | | | | | | | | According Nick Kledzik (http://llvm.org/bugs/show_bug.cgi?id=19430#c2): "... mach-o no longer needs names in the __eh_frame section (and has not for years)." Iain Sandoe confirms it is also unnecessary for their old darwin support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211500 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: mark UBFX as not allowing PC.Tim Northover2014-06-23
| | | | | | | | | Strictly, it's unpredictable. But we don't quite model that yet and an error is better than ignoring the issue. This one somehow got left out before though. rdar://problem/15997748 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211490 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: adjust text section flags for WoASaleem Abdulrasool2014-06-22
| | | | | | | | | | | | | | | | | | | | | | | Correct the section flags for code built for Windows on ARM with `-ffunction-sections`. Windows on ARM uses solely Thumb-2 instructions, and indicates that the function is thumb by placing it in a text section that has IMAGE_SCN_MEM_16BIT flag set. When we encounter a .section directive, a new section is constructed. This may be a text segment. In order to identify that we need the additional flag, expose the target triple through the ObjectFileInfo as this information is lost otherwise. Since any modern ARM targeting environment on Windows would be Thumb-2 (Windows ARM NT or Windows Embedded Compact), introducing a new flag to indicate the section attribute seems to be a bit overkill. Simply depend on the target triple. Since there is one location that this information is currently needed, creating a target specific assembly parser and delegating the parsing of section switches also feels a bit heavy handed. If it turns out that this information ends up changing additional behaviour, then it may be worth considering that alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211481 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce a Lit feature "debug_frame" and apply it to ↵NAKAMURA Takumi2014-06-22
| | | | | | | | llvm/test/MC/ELF/cfi-version.ll. .debug_frame is not emitted for targeting Windows x64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211466 91177308-0d34-0410-b5e6-96231b3b80d8
* Report error for non-zero data in .bssWeiming Zhao2014-06-22
| | | | | | | | | | | | | User may initialize a var with non-zero value and specify .bss section. E.g. : int a __attribute__((section(".bss"))) = 2; This patch converts an assertion to error report for better user experience. Differential Revision: http://reviews.llvm.org/D4199 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211455 91177308-0d34-0410-b5e6-96231b3b80d8
* Always use a temp symbol for CIE.Rafael Espindola2014-06-20
| | | | | | Fixes pr19185. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211423 91177308-0d34-0410-b5e6-96231b3b80d8
* Use compact unwind for the iOS simulator.Rafael Espindola2014-06-20
| | | | | | Another step in fixing pr19185. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211416 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't produce eh_frame relocations when targeting the IOS simulator.Rafael Espindola2014-06-20
| | | | | | First step for fixing pr19185. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211404 91177308-0d34-0410-b5e6-96231b3b80d8
* ps][mips64r6] Added LSA/DLSA instructionsZoran Jovanovic2014-06-20
| | | | | | | Differential Revision: http://reviews.llvm.org/D3897 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211346 91177308-0d34-0410-b5e6-96231b3b80d8
* Since we're using DW_AT_string rather than DW_AT_strp for debug_infoEric Christopher2014-06-19
| | | | | | | | for assembly files we can't depend on the offset within the section after a string since it could be different between producers etc. Relax these tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211308 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix this test a little harder - use llc_dwarf to make sure we don'tEric Christopher2014-06-19
| | | | | | try to execute it on windows. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211298 91177308-0d34-0410-b5e6-96231b3b80d8
* Relax this test a bit, we don't need the full contents of theEric Christopher2014-06-19
| | | | | | frame section to match, just the version for this test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211293 91177308-0d34-0410-b5e6-96231b3b80d8
* MCNullStreamer: assign file IDs to resolve crashes and errorsAlp Toker2014-06-19
| | | | | | | | | | Use the MCStreamer base implementations for file ID tracking instead of overriding them as no-ops. Avoids assertions when streaming Dwarf debug info, and fixes ASM parsing of loc and file directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211282 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests for r211273Oliver Stannard2014-06-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211279 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit DWARF3 call frame information when DWARF3+ debug info is requestedOliver Stannard2014-06-19
| | | | | | | | | | | | | | | | | | Currently, llvm always emits a DWARF CIE with a version of 1, even when emitting DWARF 3 or 4, which both support CIE version 3. This patch makes it emit the newer CIE version when we are emitting DWARF 3 or 4. This will not reduce compatibility, as we already emit other DWARF3/4 features, and is worth doing as the DWARF3 spec removed some ambiguities in the interpretation of call frame information. It also fixes a minor bug where the "return address" field of the CIE was encoded as a ULEB128, which is only valid when the CIE version is 3. There are no test changes for this, because (as far as I can tell) none of the platforms that we test have a return address register with a DWARF register number >127. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211272 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Implementation of dli.Matheus Almeida2014-06-19
| | | | | | | | | | | | Patch by David Chisnall His work was sponsored by: DARPA, AFRL Some small modifications to the original patch: we now error if it's not possible to expand an instruction (mips-expansions-bad.s has some examples). Added some comments to the expansions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211271 91177308-0d34-0410-b5e6-96231b3b80d8
* MS asm: Properly handle quoted symbol namesDavid Majnemer2014-06-19
| | | | | | | | | | | | | We would get confused by '@' characters in symbol names, we would mistake the text following them for the variant kind. When an identifier a string, the variant kind will never show up inside of it. Instead, check to see if there is a variant following the string. This fixes PR19965. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211249 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: do not add comment string to the AsmToken in AsmLexer::LexLineCommentSaleem Abdulrasool2014-06-18
| | | | | | | | Fixes macros with varargs if the macro instantiation has a trailing comment. Patch by Janne Grunau! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211219 91177308-0d34-0410-b5e6-96231b3b80d8
* MCAsmParser: full support for gas' '.if{cond} expression' directivesSaleem Abdulrasool2014-06-18
| | | | | | Patch by Janne Grunau! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211218 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] SYNC $stype instruction was added in Mips32Matheus Almeida2014-06-18
| | | | | | | but SYNC with an implied operand ($stype = 0) is valid since Mips2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211185 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] AVX512: Add non-temporal storesAdam Nemet2014-06-18
| | | | | | | | | | | Note that I followed the AVX2 convention here and didn't add LLVM intrinsics for stores. These can be generated with the nontemporal hint on LLVM IR stores (see new test). The GCC builtins are lowered directly into nontemporal stores. <rdar://problem/17082571> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211176 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] AVX512: Specify compressed displacement for vmovntdqaAdam Nemet2014-06-18
| | | | | | | Use the max 64-bit element size with EVEX_CD8. This should work since element size is ignored for a full-vector access (FVM). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211175 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix expansion of memory operation if destination register is not a GPR.Matheus Almeida2014-06-18
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The assembler tries to reuse the destination register for memory operations whenever it can but it's not possible to do so if the destination register is not a GPR. Example: ldc1 $f0, sym should expand to: lui $at, %hi(sym) ldc1 $f0, %lo(sym)($at) It's entirely wrong to expand to: lui $f0, %hi(sym) ldc1 $f0, %lo(sym)($f0) Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4173 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211169 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Report correct location when "erroring" about the use of $at when ↵Matheus Almeida2014-06-18
| | | | | | | | | | | | | | it's not available. Summary: This removes the FIXMEs from test/MC/Mips/mips-noat.s. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4172 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211168 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Add BLTC and BLTUC instructionsZoran Jovanovic2014-06-18
| | | | | | | Differential Revision: http://reviews.llvm.org/D3923 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211167 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Access $at only if necessary.Matheus Almeida2014-06-18
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch doesn't really change the logic behind expandMemInst but it allows us to assemble .S files that use .set noat with some macros. For example: .set noat lw $k0, offset($k1) Can expand to: lui $k0, %hi(offset) addu $k0, $k0, $k1 lw $k0, %lo(offset)($k0) with no need to access $at. Reviewers: dsanders, vmedic Reviewed By: dsanders, vmedic Differential Revision: http://reviews.llvm.org/D4159 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211165 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Update MipsAsmParser so that it's possible to handle immediates that ↵Matheus Almeida2014-06-18
| | | | | | | | | | | | start with the binary operator NOT (~). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4158 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211163 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Implement alias for 'and' and 'or' instructions for all ISAs.Matheus Almeida2014-06-18
| | | | | | | | | | | | | | | Summary: Examples: and $2, 4 <=> andi $2, $2, 4 or $2, 4 <=> ori $2, $2, 4 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4155 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211161 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Remove the last usage of parseRegister from MipsAsmParser.Matheus Almeida2014-06-18
| | | | | | | | | | | | | | Summary: Added negative test case so that we can be sure we handle erroneous situations while parsing the .cpsetup directive. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3681 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211160 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] ssnop is deprecated on MIPS32r6/MIPS64r6Daniel Sanders2014-06-16
| | | | | | | | | | | | Summary: Depends on D4120 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: zoran.jovanovic, vmedic Differential Revision: http://reviews.llvm.org/D4121 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211021 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6Daniel Sanders2014-06-16
| | | | | | | | | | | | | | | | | Summary: There is no change to the restrictions, just the result register is stored once in the encoding rather than twice. The rt field is zero in MIPS32r6/MIPS64r6. Depends on D4119 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4120 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211019 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.Daniel Sanders2014-06-16
| | | | | | | | | | | | | | | | | | | | | Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211018 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates ↵Daniel Sanders2014-06-16
| | | | | | | | | | | | | | | | | | | | | rather than 16-bit in MIPS32r6/MIPS64r6 Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211012 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Relocation R_MIPS_PC18_S3Zoran Jovanovic2014-06-13
| | | | | | | Differential Revision: http://reviews.llvm.org/D3890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210908 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add cache and pref instructionsDaniel Sanders2014-06-13
| | | | | | | | | | | | | | | | | | | Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210900 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] bc1any[24] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-13
| | | | | | | | | | | | | | Summary: These MIPS-3D instructions have never been implemented in LLVM so we only add testcases. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4115 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210899 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal ↵Daniel Sanders2014-06-13
| | | | | | | | | | | | | | | | | | | | | | | | | | is a normal instruction Summary: b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias for 'bgezal $zero, $offset') still remains with the same encoding it had prior to MIPS32r6/MIPS64r6. Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo. No changes were required to the CodeGen test that looks for BAL (test/CodeGen/Mips/longbranch.ll) since the new instruction has the same syntax. Depends on D4113 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4114 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210898 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] daddi is not available on MIPS64r6Daniel Sanders2014-06-13
| | | | | | | | | | | | | | | | | | Summary: It's not emitted by the code generator so we only need assembler tests. Also added missing daddi aliases from dsub mnemonics, and removed a couple duplicate dsub tests. Depends on D4112 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4113 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210897 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-12
| | | | | | | | | | | | | | | | | | | | Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210787 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] bc2[ft] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-12
| | | | | | | | | | | | | | | | Summary: These instructions are not implemented for any MIPS ISA so we only need testcases. Depends on D4110 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4111 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210786 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-16 01:03:45 +0000