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* Re-work bit/bits value resolving in tblgenMichael Liao2012-09-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - This patch is inspired by the failure of the following code snippet which is used to convert enumerable values into encoding bits to improve the readability of td files. class S<int s> { bits<2> V = !if(!eq(s, 8), {0, 0}, !if(!eq(s, 16), {0, 1}, !if(!eq(s, 32), {1, 0}, !if(!eq(s, 64), {1, 1}, {?, ?})))); } Later, PR8330 is found to report not exactly the same bug relevant issue to bit/bits values. - Instead of resolving bit/bits values separately through resolveBitReference(), this patch adds getBit() for all Inits and resolves bit value by resolving plus getting the specified bit. This unifies the resolving of bit with other values and removes redundant logic for resolving bit only. In addition, BitsInit::resolveReferences() is optimized to take advantage of this origanization by resolving VarBitInit's variable reference first and then getting bits from it. - The type interference in '!if' operator is revised to support possible combinations of int and bits/bit in MHS and RHS. - As there may be illegal assignments from integer value to bit, says assign 2 to a bit, but we only check this during instantiation in some cases, e.g. bit V = !if(!eq(x, 17), 0, 2); Verbose diagnostic message is generated when invalid value is resolveed to help locating the error. - PR8330 is fixed as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163360 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips standalone assembler memory instruction support.Jack Carter2012-09-06
| | | | | | | | | | | This includes sb,sc,sh,sw,lb,lw,lbu,lh,lhu,ll,lw Test case included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163346 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow overlaps between virtreg and physreg live ranges.Jakob Stoklund Olesen2012-09-06
| | | | | | | | | | | | | | | | | The RegisterCoalescer understands overlapping live ranges where one register is defined as a copy of the other. With this change, register allocators using LiveRegMatrix can do the same, at least for copies between physical and virtual registers. When a physreg is defined by a copy from a virtreg, allow those live ranges to overlap: %CL<def> = COPY %vreg11:sub_8bit; GR32_ABCD:%vreg11 %vreg13<def,tied1> = SAR32rCL %vreg13<tied0>, %CL<imp-use,kill> We can assign %vreg11 to %ECX, overlapping the live range of %CL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163336 91177308-0d34-0410-b5e6-96231b3b80d8
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-06
| | | | | | Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163323 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover2012-09-06
| | | | | | | | instructions. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163321 91177308-0d34-0410-b5e6-96231b3b80d8
* BasicAA: Recognize cyclic NoAlias phisArnold Schwaighofer2012-09-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhances basic alias analysis to recognize phis whose first incoming values are NoAlias and whose other incoming values are just the phi node itself through some amount of recursion. Example: With this change basicaa reports that ptr_phi and ptr_phi2 do not alias each other. bb: ptr = ptr2 + 1 loop: ptr_phi = phi [bb, ptr], [loop, ptr_plus_one] ptr2_phi = phi [bb, ptr2], [loop, ptr2_plus_one] ... ptr_plus_one = gep ptr_phi, 1 ptr2_plus_one = gep ptr2_phi, 1 This enables the elimination of one load in code like the following: extern int foo; int test_noalias(int *ptr, int num, int* coeff) { int *ptr2 = ptr; int result = (*ptr++) * (*coeff--); while (num--) { *ptr2++ = *ptr; result += (*coeff--) * (*ptr++); } *ptr = foo; return result; } Part 2/2 of fix for PR13564. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163319 91177308-0d34-0410-b5e6-96231b3b80d8
* Use correct part of complex operand to encode VST1 alignment.Tim Northover2012-09-06
| | | | | | Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163318 91177308-0d34-0410-b5e6-96231b3b80d8
* BasicAA: GEPs of NoAlias'ing base ptr with equivalent indices are NoAliasArnold Schwaighofer2012-09-06
| | | | | | | | | | | | | | If we can show that the base pointers of two GEPs don't alias each other using precise analysis and the indices and base offset are equal then the two GEPs also don't alias each other. This is primarily needed for the follow up patch that analyses NoAlias'ing PHI nodes. Part 1/2 of fix for PR13564. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163317 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable stack coloring by default in order to resolve the i386 failures.Nadav Rotem2012-09-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163316 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX2 optimization.Elena Demikhovsky2012-09-06
| | | | | | Added generation of VPSHUB instruction for <32 x i8> vector shuffle when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163312 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the test by specifying an exact cpu model.Nadav Rotem2012-09-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163307 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix switch_to_lookup_table.ll test from r163302.Hans Wennborg2012-09-06
| | | | | | | | The lookup tables did not get built in a deterministic order. This makes them get built in the order that the corresponding phi nodes were found. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163305 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve codegen for BUILD_VECTORs on ARM.James Molloy2012-09-06
| | | | | | | | If we have a BUILD_VECTOR that is mostly a constant splat, it is often better to splat that constant then insertelement the non-constant lanes instead of insertelementing every lane from an undef base. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163304 91177308-0d34-0410-b5e6-96231b3b80d8
* Build lookup tables for switches (PR884)Hans Wennborg2012-09-06
| | | | | | | | | | | | | | | | | | | | | | This adds a transformation to SimplifyCFG that attemps to turn switch instructions into loads from lookup tables. It works on switches that are only used to initialize one or more phi nodes in a common successor basic block, for example: int f(int x) { switch (x) { case 0: return 5; case 1: return 4; case 2: return -2; case 5: return 7; case 6: return 9; default: return 42; } This speeds up the code by removing the hard-to-predict jump, and reduces code size by removing the code for the jump targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163302 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-06
| | | | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate ↵James Molloy2012-09-06
| | | | | | to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163298 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for converting stores of subvector_extracts of lower 128-bits ↵Craig Topper2012-09-06
| | | | | | of a 256-bit vector to VMOVAPSmr/VMOVUPSmr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163292 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Enable MCJIT tests on Darwin."Jim Grosbach2012-09-06
| | | | | | | | This reverts commit 163278. Works OK on x86_64, but not i386. Will re-enable when that's cleared up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163290 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable MCJIT tests on Darwin.Jim Grosbach2012-09-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163278 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips specific llvm assembler support for branch and jump instructions.Jack Carter2012-09-06
| | | | | | | | | Test case included. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163277 91177308-0d34-0410-b5e6-96231b3b80d8
* Use predication instead of pseudo-opcodes when folding into MOVCC.Jakob Stoklund Olesen2012-09-05
| | | | | | | | | | | | | | | | | | | | Now that it is possible to dynamically tie MachineInstr operands, predicated instructions are possible in SSA form: %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR Becomes a predicated SUBri with a tied imp-use: SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0> This means that any instruction that is safe to move can be folded into a MOVCC, and the *CC pseudo-instructions are no longer needed. The test case changes reflect that Thumb2SizeReduce recognizes the predicated instructions. It didn't understand the pseudos. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing file for test.Nick Lewycky2012-09-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163272 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach libObject about some more ELF relocations. llvm-objdump -r now knowsNick Lewycky2012-09-05
| | | | | | | every relocation in C++ hello world built with debug info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163271 91177308-0d34-0410-b5e6-96231b3b80d8
* JumpThreading: when default destination is the destination of some cases in aManman Ren2012-09-05
| | | | | | | | | | switch, make sure we include the value for the cases when calculating edge value from switch to the default destination. rdar://12241132 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163270 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips specific llvm assembler support for ALU instructions. This includesJack Carter2012-09-05
| | | | | | | | | register support. Test case included. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163268 91177308-0d34-0410-b5e6-96231b3b80d8
* Strip old MachineInstrs *after* we know we can put them back.Tim Northover2012-09-05
| | | | | | | | Previous patch accidentally decided it couldn't convert a VFP to a NEON instruction after it had already destroyed the old one. Not a good move. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163230 91177308-0d34-0410-b5e6-96231b3b80d8
* LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access thePranav Bhandarkar2012-09-05
| | | | | | | | | | | | | | | | | subreg_hireg of register pair Rp. * lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New DenseMap similar to PeepholeMap that additionally records subreg info too. (runOnMachineFunction): Record information in PeepholeDoubleRegsMap and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to the instruction Rx = COPY Rp1:logreg_subreg. * test/CodeGen/Hexagon/remove_lsr.ll: New test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163214 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed the DAG combiner to better handle the folding of AND nodes for vector ↵Silviu Baranga2012-09-05
| | | | | | types. The previous code was making the assumption that the length of the bitmask returned by isConstantSplat was equal to the size of the vector type. Now we first make sure that the splat value has at least the length of the vector lane type, then we only use as many fields as we have available in the splat value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163203 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix UseInitArray option for MIPS target.Logan Chien2012-09-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163193 91177308-0d34-0410-b5e6-96231b3b80d8
* Make provenance checking conservative in cases whenDan Gohman2012-09-04
| | | | | | | | | pointers-to-strong-pointers may be in play. These can lead to retains and releases happening in unstructured ways, foiling the optimizer. This fixes rdar://12150909. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163180 91177308-0d34-0410-b5e6-96231b3b80d8
* Move tie checks into MachineVerifier::visitMachineOperand.Jakob Stoklund Olesen2012-09-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163152 91177308-0d34-0410-b5e6-96231b3b80d8
* Generic Bypass Slow DivPreston Gurd2012-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | - CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
* Porting Hexagon MI Scheduler to the new API.Sergei Larin2012-09-04
| | | | | | | | Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163137 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-09-04
| | | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163136 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch optimizes shuffle instruction - generates 2 instructions instead ↵Elena Demikhovsky2012-09-04
| | | | | | | | | | | | | | | | | | | | | of 4. Since this specific shuffle is widely used in many workloads we have ~10% performance on them. shufflevector <8 x float> %A, <8 x float> %B, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> vmovaps (%rdx), %ymm0 vshufps $8, %ymm0, %ymm0, %ymm0 vmovaps (%rcx), %ymm1 vshufps $8, %ymm0, %ymm1, %ymm1 vunpcklps %ymm0, %ymm1, %ymm0 vmovaps (%rcx), %ymm0 vmovsldup (%rdx), %ymm1 vblendps $85, %ymm0, %ymm1, %ymm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163134 91177308-0d34-0410-b5e6-96231b3b80d8
* LICM may hoist an instruction with undefined behavior above a trap.Nadav Rotem2012-09-04
| | | | | | | | | | | | Scan the body of the loop and find instructions that may trap. Use this information when deciding if it is safe to hoist or sink instructions. Notice that we can optimize the search of instructions that may throw in the case of nested loops. rdar://11518836 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163132 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for fetching inlining context (stack of source code locations)Alexey Samsonov2012-09-04
| | | | | | | | | | | | by instruction address from DWARF. Add --inlining flag to llvm-dwarfdump to demonstrate and test this functionality, so that "llvm-dwarfdump --inlining --address=0x..." now works much like "addr2line -i 0x...", provided that the binary has debug info (Clang's -gline-tables-only *is* enough). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163128 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix more fallout from r158919, similar to PR13547.Bob Wilson2012-09-03
| | | | | | | | | This code used to only handle malloc-like calls, which do not read memory. r158919 changed it to check isNoAliasFn(), which includes strdup-like and realloc-like calls, but it was not checking for dependencies on the memory read by those calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163106 91177308-0d34-0410-b5e6-96231b3b80d8
* escape special char when handling CXX_FOR_OCAMLOPTNuno Lopes2012-09-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163098 91177308-0d34-0410-b5e6-96231b3b80d8
* fix test's RUN linesNuno Lopes2012-09-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163097 91177308-0d34-0410-b5e6-96231b3b80d8
* Not all targets have efficient ISel code generation for select instructions.Nadav Rotem2012-09-02
| | | | | | | | | | | For example, the ARM target does not have efficient ISel handling for vector selects with scalar conditions. This patch adds a TLI hook which allows the different targets to report which selects are supported well and which selects should be converted to CF duting codegen prepare. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163093 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopRotation: Make the brute force DomTree update more brute force.Benjamin Kramer2012-09-02
| | | | | | | | | | | | | | We update until we hit a fixpoint. This is probably slow but also slightly simplifies the code. It should also fix the occasional invalid domtrees observed when building with expensive checking. I couldn't find a case where this had a measurable slowdown, but if someone finds a pathological case where it does we may have to find a cleverer way of updating dominators here. Thanks to Duncan for the test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163091 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate better select code by allowing the target to use scalar select, and ↵Nadav Rotem2012-09-02
| | | | | | not sign-extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163086 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Take account of boolean vector contents when promoting a build ↵Pete Cooper2012-09-01
| | | | | | | | | | | | | | vector from i1 to some other type. rdar://problem/12210060" This reverts commit 5dd9e214fb92847e947f9edab170f9b4e52b908f. Thanks to Duncan for explaining how this should have been done. Conflicts: test/CodeGen/X86/vec_select.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163064 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Thumb2 fixup kind in the integrated-as.Logan Chien2012-09-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163063 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DAG combine a number of tricks to simplify FMA expressions in ↵Owen Anderson2012-09-01
| | | | | | fast-math mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163051 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/fp-fast.ll: Suppress FMA4 on AMD Bulldozer host, ↵NAKAMURA Takumi2012-09-01
| | | | | | corresponding to r162999. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163041 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Atom bots for r163036.Manman Ren2012-09-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163040 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: when constructing VZEXT_LOAD from other loads, make sure itsManman Ren2012-08-31
| | | | | | | | | | | | output chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://11457792 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163036 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark FMA4 instructions as commutable and add them to the folding tables.Craig Topper2012-08-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163035 91177308-0d34-0410-b5e6-96231b3b80d8
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