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* Fix spelling, grammar, and match naming convention for test files.Eric Christopher2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193130 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add the constraint to NEON scalar mla/mls instructions.Chad Rosier2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193117 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyCFG: Don't duplicate calls to functions marked noduplicate v2Tom Stellard2013-10-21
| | | | | | | v2: - Use CI->cannotDuplicate() git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193115 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix CodeGen for vectors of pointers with address spaces.Matt Arsenault2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193112 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix CodeGen for different size address space GEPsMatt Arsenault2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193111 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach SimplifyCFG about address spacesMatt Arsenault2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193104 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix creating bitcasts between address spaces in SCEV.Matt Arsenault2013-10-21
| | | | | | | | The test before wasn't successfully testing this since it was missing the datalayout piece to change the size of the second address space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193102 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 vector element shift-by-immediate instructions take i8 immediates. MakeLang Hames2013-10-21
| | | | | | | | | | | | | | | | the instruction defenitions and ISEL reflect this. Prior to this patch these instructions took an i32i8imm, and the high bits were dropped during encoding. This led to incorrect behavior for shifts by immediates higher than 255. This patch fixes that issue by detecting large immediate shifts and returning constant zero (for logical shifts) or capping the shift amount at an encodable value (for arithmetic shifts). Fixes <rdar://problem/14968098> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193096 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize more linkonce_odr values during LTO.Rafael Espindola2013-10-21
| | | | | | | | | | | When a linkonce_odr value that is on the dso list is not unnamed_addr we can still look to see if anything is actually using its address. If not, it is safe to hide it. This patch implements that by moving GlobalStatus to Transforms/Utils and using it in Internalize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193090 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Hash DW_FORM_GNU_str_index as a string.David Blaikie2013-10-21
| | | | | | | | | | Found while adding type safety to the various DWARF enumerations (form, attribute, tag, etc) that caused Clang to warn on an incompletely covered switch. Converting the comment to a default/unreachable uncovered this case of an unsupported form encoding. Seems we were skipping fission strings entirely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193089 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: MUL operation lowering for v8i64Elena Demikhovsky2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193083 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission support for LD/ST instructions.Matheus Almeida2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193082 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission support for LDI instructions.Matheus Almeida2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193081 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission support for MOVE.v.Matheus Almeida2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193080 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. Matheus Almeida2013-10-21
| | | | | | | | | | These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193078 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission of SPLAT instruction.Matheus Almeida2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193077 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Fix definition of SLD instruction.Matheus Almeida2013-10-21
| | | | | | | | | The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't eliminate a partially redundant load if it's in a landing pad.Bill Wendling2013-10-21
| | | | | | | | | | | | | A landing pad can be jumped to only by the unwind edge of an invoke instruction. If we eliminate a partially redundant load in a landing pad, it will create a basic block that violates this constraint. It then leads to other problems down the line if it tries to merge that basic block with the landing pad. Avoid this by not eliminating the load in a landing pad. PR17621 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193064 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo in test's XFAIL line. Patch by Dimitry Andric!Nick Lewycky2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193063 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach simplify-cfg how to correctly create covered lookup tables for ↵Michael Gottesman2013-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | switches on iN with N >= 3. One optimization simplify-cfg performs is the converting of switches to lookup tables if the switch has > 4 cases. This is done by: 1. Finding the max/min case value and calculating the switch case range. 2. Create a lookup table basic block. 3. Perform a check in the switch's BB to see if the input value is in the switch's case range. If the input value satisfies said predicate branch to the lookup table BB, otherwise branch to the switch's default destination BB using the default value as the result. The conditional check consists of subtracting the min case value of the table from any input iN value and then ensuring that said value is unsigned less than the size of the lookup table represented as an iN value. If the lookup table is a covered lookup table, the size of the table will be N which is 0 as an iN value. Thus the comparison will be an `icmp ult` of an iN value against 0 which is always false yielding the incorrect result. This patch fixes this problem by recognizing if we have a covered lookup table and if we do, unconditionally jumps to the lookup table BB since the covering property of the lookup table implies no input values could not be handled by said BB. rdar://15268442 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193045 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit prefix data after debug and EH directives.Peter Collingbourne2013-10-20
| | | | | | | | | This ensures that the prefix data is treated as part of the function for the purpose of debug info. This provides a better debugging experience, among other things by allowing a debug info client to correctly look up a function in debug info given a function pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193042 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit DWARF line entries for all data in the instruction stream.Peter Collingbourne2013-10-20
| | | | | | | r182712 attempted to do this, but it failed to handle data emitted via EmitBytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193041 91177308-0d34-0410-b5e6-96231b3b80d8
* Perform an intelligent splice of the predecessor with the single successor.Bill Wendling2013-10-19
| | | | | | | | If the predecessor's being spliced into a landing pad, then we need the PHIs to come first and the rest of the predecessor's code to come *after* the landing pad instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193035 91177308-0d34-0410-b5e6-96231b3b80d8
* Update PPC loop tests after SCEV non-unit-stride checkin r193015.Andrew Trick2013-10-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193021 91177308-0d34-0410-b5e6-96231b3b80d8
* SCEV should use NSW to get trip count for positive nonunit stride loops.Andrew Trick2013-10-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SCEV currently fails to compute loop counts for nonunit stride loops. This comes up frequently. It prevents loop optimization and forces vectorization to insert extra loop checks. For example: void foo(int n, int *x) { for (int i = 0; i < n; i += 3) { x[i] = i; x[i+1] = i+1; x[i+2] = i+2; } } We need to properly handle the case in which limit > INT_MAX-stride. In the above case: n > INT_MAX-3. In this case the loop counter will step beyond the limit and overflow at the same time. However, knowing that signed integer overlow in undefined, we can assume the loop test behavior is arbitrary after overflow. This obeys both C undefined behavior rules, and the more strict LLVM poison value rules. I'm finally fixing this in response to Hal Finkel's persistence. The most probable reason that we never optimized this before is that we were being careful to handle case where the developer expected a side-effect free infinite loop relying on overflow: for (int i = 0; i < n; i += s) { ++j; } return j; If INT_MAX+1 is a multiple of s and n > INT_MAX-s, then we might expect an infinite loop. However there are plenty of ways to achieve this effect without relying on undefined behavior of signed overflow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193015 91177308-0d34-0410-b5e6-96231b3b80d8
* [Support][YAML] Add support for accessing tags and tag handle substitution.Michael J. Spencer2013-10-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193004 91177308-0d34-0410-b5e6-96231b3b80d8
* MC asm parser: allow ?'s in symbol names, and handle @'s in names in MS asmHans Wennborg2013-10-18
| | | | | | | | | | | | | | | | | | | | This is another (final?) stab at making us able to parse our own asm output on Windows. Symbols on Windows often contain @'s and ?'s in their names. Our asm parser didn't like this. ?'s were not allowed, and @'s were intepreted as trying to reference PLT/GOT/etc. We can't just add quotes around the bad names, since e.g. for MinGW, we use gas to assemble, and it doesn't like quotes in some places (notably in .def directives). This commit makes us allow ?'s in symbol names, and @'s in symbol names for MS assembly. Differential Revision: http://llvm-reviews.chandlerc.com/D1978 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193000 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r192957David Majnemer2013-10-18
| | | | | | | Forgot to 'svn add' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192978 91177308-0d34-0410-b5e6-96231b3b80d8
* [PATCH] Fix PR17168 (DAG scheduler inserts DBG_VALUE before PHI with fast-isel)Bill Schmidt2013-10-18
| | | | | | | | | | | | | | | | | | | | | | | | | PR17168 describes a test case that fails when compiling for debug with fast-isel. Investigation showed that the test was failing because a DBG_VALUE machine instruction was placed prior to a PHI. For this problem to occur requires the following: * Compile for debug * Compile with fast-isel * In a block B, fast-isel must partially succeed before punting to DAG-isel * B must start with a PHI * The first unhandled node in the DAG must not generate a machine instruction * A debug value with an order less than that of that first node exists When all of these circumstances apply, the existing test that an instruction was not inserted won't fire. Currently it tests whether the block is empty, or whether the last instruction generated is a phi. When fast-isel has partially succeeded, the last instruction generated will not be a phi. Instead, we need to check whether the current insert position is immediately following a phi. This patch adds that check, and adds the test case from the PR as a regression test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192976 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hint disassembly syntax for 16-bit Thumb hint instructions.Richard Barton2013-10-18
| | | | | | | | Patch by Artyom Skrobov git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192972 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar extract narrow instructions.Chad Rosier2013-10-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192970 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hardware division as a default feature on Cortex-A15. Also add test ↵Silviu Baranga2013-10-18
| | | | | | cases to check this, and change diagnostics for the hwdiv-arm feature to something useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192963 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added a regression test that depended on multiple patches to pass.Daniel Sanders2013-10-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192961 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Re-commit r192758 - MC: quote tricky symbol names in asm output"Hans Wennborg2013-10-18
| | | | | | | | | | | | | | | | | This caused the clang-native-mingw32-win7 buildbot to break. The assembler was complaining about the following lines that were showing up in the asm for CrashRecoveryContext.cpp: movl $"__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4", 4(%eax) calll "_AddVectoredExceptionHandler@8" .def "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4"; "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4": calll "_RemoveVectoredExceptionHandler@4" Reverting for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192940 91177308-0d34-0410-b5e6-96231b3b80d8
* 17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targetsDavid Peixotto2013-10-17
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit implements the correct lowering of the COPY_STRUCT_BYVAL_I32 pseudo-instruction for thumb1 targets. Previously, the lowering of COPY_STRUCT_BYVAL_I32 generated the post-increment forms of ldr/ldrh/ldrb instructions. Thumb1 does not have the post-increment form of these instructions so the generated assembly contained invalid instructions. Passing the generated assembly to gcc caused it to complain with an error like this: Error: cannot honor width suffix -- `ldrb r3,[r0],#1' and the integrated assembler would generate an object file with an invalid instruction encoding. This commit contains a small test case that demonstrates the problem with thumb1 targets as well as an expanded test case that more throughly tests the lowering of byval struct passing for arm, thumb1, and thumb2 targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192916 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar three register different instructionChad Rosier2013-10-17
| | | | | | | | class. The instruction class includes the signed saturating doubling multiply-add long, signed saturating doubling multiply-subtract long, and the signed saturating doubling multiply long instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8
* Add testcase to make sure we don't generate a compact unwind section for ELF ↵Bill Wendling2013-10-17
| | | | | | | | binaries. This tests r190354. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192903 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added lsa instructionDaniel Sanders2013-10-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192895 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix tests not to depend on specific regalloc or instruction order.Benjamin Kramer2013-10-17
| | | | | | They were failing with -mcpu=atom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192890 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix r192888: test/CodeGen/Mips/msa/3r_ld_st.ll should have been deletedDaniel Sanders2013-10-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192889 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace sra with srl if a single sign bit is requiredRichard Sandiford2013-10-17
| | | | | | | E.g. (and (sra (i32 x) 31) 2) -> (and (srl (i32 x) 30) 2). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192884 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix edge condition in DAGCombiner to improve codegen of shift sequences.Andrea Di Biagio2013-10-17
| | | | | | | | | | | | | When canonicalizing dags according to the rule (shl (zext (shr X, c1) ), c1) ==> (zext (shl (shr X, c1), c1)) remember to add the new shl dag to the DAGCombiner worklist of nodes. If we don't explicitly add it to the worklist of nodes to visit, we may not trigger later on the rule that folds the shift left + logical shift right into a AND instruction with bitmask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192883 91177308-0d34-0410-b5e6-96231b3b80d8
* Changing DebugInfoFinder to iterate over all the compile units.Michael Kuperstein2013-10-17
| | | | | | | | Solves http://llvm.org/bugs/show_bug.cgi?id=17507 Committed on behalf of alon.mishne@intel.com git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192879 91177308-0d34-0410-b5e6-96231b3b80d8
* tsan: implement no_sanitize_thread attributeDmitry Vyukov2013-10-17
| | | | | | | | | If a function has no_sanitize_thread attribute, do not instrument memory accesses in it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192871 91177308-0d34-0410-b5e6-96231b3b80d8
* x86: Move bitcasts outside concat_vector.Jim Grosbach2013-10-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider the following: typedef unsigned short ushort4U __attribute__((ext_vector_type(4), aligned(2))); typedef unsigned short ushort4 __attribute__((ext_vector_type(4))); typedef unsigned short ushort8 __attribute__((ext_vector_type(8))); typedef int int4 __attribute__((ext_vector_type(4))); int4 __bbase_cvt_int(ushort4 v) { ushort8 a; a.lo = v; return _mm_cvtepu16_epi32(a); } This generates the, not unreasonable, IR: define <4 x i32> @foo0(double %v.coerce) nounwind ssp { %tmp = bitcast double %v.coerce to <4 x i16> %tmp1 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> <i32 %0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %tmp2 = tail call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp1) ret <4 x i32> %tmp2 } The problem is when type legalization gets hold of the v4i16. It legalizes that by spilling to the stack, then doing a zero-extending load. Things go even more silly from there, ending up with something like: _foo0: movsd %xmm0, -8(%rsp) <== Spill to the stack. movq -8(%rsp), %xmm0 <== Reload it right back out. pmovzxwd %xmm0, %xmm1 <== Here's what we actually asked for. pblendw $1, %xmm1, %xmm0 <== We don't need this at all pmovzxwd %xmm0, %xmm0 <== We already did this ret The v8i8 to v8i16 zext intrinsic gives even worse results, with two table lookups via pshufb instructions(!!). To avoid all that, we can move the bitcasting until after we've formed the wider (legal) vector type. Then our normal codegen flows along nicely and we get the expected: _foo0: pmovzxwd %xmm0, %xmm0 ret rdar://15245794 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192866 91177308-0d34-0410-b5e6-96231b3b80d8
* According to the dwarf standard pubnames and pubtypes for languagesEric Christopher2013-10-17
| | | | | | | | | | | like C++ should be the fully qualified names for the type. Add a routine that does a language specific context walk to build up the qualified name and use it when we add types/names to the tables. Expand the gnu pubnames testcase as it's the most complex to make sure that qualified types are also being added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192865 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the subprogram DIEs to the context they're created with onlyEric Christopher2013-10-17
| | | | | | | if they're a declaration, otherwise they're owned by the compile unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192861 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-commit r192758 - MC: quote tricky symbol names in asm outputHans Wennborg2013-10-17
| | | | | | | | | | | | | | | | | | | | | | | | | | The reason this got reverted was that the @feat.00 symbol which was emitted for every TU became quoted, and on cygwin/mingw we use the gas assembler which couldn't handle the quotes. This commit fixes the problem by only emitting @feat.00 for win32, where we use clang -cc1as to assemble. gas would just drop this symbol anyway, so there is no loss there. With @feat.00 gone, there shouldn't be quoted symbols showing up on cygwin since it uses the Itanium ABI, which doesn't put these funny characters in symbols. > Because of win32 mangling, we produce symbol and section names with > funny characters in them, most notably @ characters. > > MC would choke on trying to parse its own assembly output. This patch addresses > that by: > > - Making @ trigger quoting of symbol names > - Also quote section names in the same way > - Just parse section names like other identifiers (to allow for quotes) > - Don't assume @ signifies a symbol variant if it is in a string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192859 91177308-0d34-0410-b5e6-96231b3b80d8
* DIEHash: Use DW_FORM_sdata for integers, per spec.David Blaikie2013-10-16
| | | | | | | This allows us to produce the same hash as GCC for at least some simple examples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192855 91177308-0d34-0410-b5e6-96231b3b80d8
* Update test case due to DIE hashing in r192836David Blaikie2013-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192850 91177308-0d34-0410-b5e6-96231b3b80d8
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