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* Allow vectorization of bit intrinsics in BB Vectorizer.Karthik Bhat2014-04-25
| | | | | | | | This patch adds support for vectorization of bit intrinsics such as bswap,ctpop,ctlz,cttz. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207174 91177308-0d34-0410-b5e6-96231b3b80d8
* ProfileData: Treat missing function counts as malformedJustin Bogner2014-04-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207172 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "This reapplies r207130 with an additional testcase+and a missing ↵Adrian Prantl2014-04-25
| | | | | | | | check for" Typo in testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207166 91177308-0d34-0410-b5e6-96231b3b80d8
* This reapplies r207130 with an additional testcase+and a missing check forAdrian Prantl2014-04-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AllocaInst that was missing in one location. Debug info for optimized code: Support variables that are on the stack and described by DBG_VALUEs during their lifetime. Previously, when a variable was at a FrameIndex for any part of its lifetime, this would shadow all other DBG_VALUEs and only a single fbreg location would be emitted, which in fact is only valid for a small range and not the entire lexical scope of the variable. The included dbg-value-const-byref testcase demonstrates this. This patch fixes this by Local - emitting dbg.value intrinsics for allocas that are passed by reference - dropping all dbg.declares (they are now fully lowered to dbg.values) SelectionDAG - renamed constructors for SDDbgValue for better readability. - fix UserValue::match() to handle indirect values correctly - not inserting an MMI table entries for dbg.values that describe allocas. - lowering dbg.values that describe allocas into *indirect* DBG_VALUEs. CodeGenPrepare - leaving dbg.values for an alloca were they are (see comment) Other - regenerated/updated instcombine.ll testcase and included source rdar://problem/16679879 http://reviews.llvm.org/D3374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207165 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Debug info for optimized code: Support variables that are on the ↵Adrian Prantl2014-04-25
| | | | | | | | stack and" This reverts commit 207130 for buildbot breakage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207162 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Debug info: Let dbg.values inserted by LowerDbgDeclare inherit the ↵Adrian Prantl2014-04-24
| | | | | | | | location" This reverts commit 207130 for buildbot breakage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207159 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Don't transform shifts into ands when the sign bit is tested.Benjamin Kramer2014-04-24
| | | | | | Should unbreak MultiSource/Benchmarks/mediabench/g721/g721encode/encode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207145 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'musttail' marker to call instructionsReid Kleckner2014-04-24
| | | | | | | | | | | | This is similar to the 'tail' marker, except that it guarantees that tail call optimization will occur. It also comes with convervative IR verification rules that ensure that tail call optimization is possible. Reviewers: nicholas Differential Revision: http://llvm-reviews.chandlerc.com/D3240 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207143 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix rdtsc.ll test to match r8 on win64Reid Kleckner2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207142 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug info: Let dbg.values inserted by LowerDbgDeclare inherit the locationAdrian Prantl2014-04-24
| | | | | | | | | of the dbg.value. This gets rid of tons of redundant variable DIEs in subscopes. rdar://problem/14874886, rdar://problem/16679936 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207135 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug info for optimized code: Support variables that are on the stack andAdrian Prantl2014-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | described by DBG_VALUEs during their lifetime. Previously, when a variable was at a FrameIndex for any part of its lifetime, this would shadow all other DBG_VALUEs and only a single fbreg location would be emitted, which in fact is only valid for a small range and not the entire lexical scope of the variable. The included dbg-value-const-byref testcase demonstrates this. This patch fixes this by Local - emitting dbg.value intrinsics for allocas that are passed by reference - dropping all dbg.declares (they are now fully lowered to dbg.values) SelectionDAG - renamed constructors for SDDbgValue for better readability. - fix UserValue::match() to handle indirect values correctly - not inserting an MMI table entries for dbg.values that describe allocas. - lowering dbg.values that describe allocas into *indirect* DBG_VALUEs. CodeGenPrepare - leaving dbg.values for an alloca were they are (see comment) Other - regenerated/updated instcombine-intrinsics testcase and included source rdar://problem/16679879 http://reviews.llvm.org/D3374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207130 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add support for Read Time Stamp Counter x86 builtin intrinsics.Andrea Di Biagio2014-04-24
| | | | | | | | | | | | | | | | This patch: - Adds two new X86 builtin intrinsics ('int_x86_rdtsc' and 'int_x86_rdtscp') as GCCBuiltin intrinsics; - Teaches the backend how to lower the two new builtins; - Introduces a common function to lower READCYCLECOUNTER dag nodes and the two new rdtsc/rdtscp intrinsics; - Improves (and extends) the existing x86 test 'rdtsc.ll'; now test 'rdtsc.ll' correctly verifies that both READCYCLECOUNTER and the two new intrinsics work fine for both 64bit and 32bit Subtargets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207127 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add ARM64 runs to more MC tests.Tim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207120 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too.Tim Northover2014-04-24
| | | | | | | | This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207119 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: print NEON lists with a space.Tim Northover2014-04-24
| | | | | | | This matches ARM64 behaviour, which I think is clearer. It also puts all the churn from that difference into one easily ignored commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207116 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: enable remaining MC elf tests.Tim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207112 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: allow negative addends, at least on ELF.Tim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207111 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: support relocated "TBZ/TBNZ" instructions.Tim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207110 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: support relocated ADR instructionTim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207109 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add support for :abs_gN_s: MOVZ modifiersTim Northover2014-04-24
| | | | | | We only need assembly support, so it's fairly easy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207108 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operandsTim Northover2014-04-24
| | | | | | | | | | | | | These can have different relocations in ELF. In particular both: b.eq global ldr x0, global are valid, giving different relocations. The only possible way to distinguish them is via a different fixup, so the operands had to be separated throughout the backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207105 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: enable some MC tests on ARM64Tim Northover2014-04-24
| | | | | | | This will also (as with CodeGen) disable testing when the ARM64 backend is not present. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207104 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: port bitfield test to ARM64.Tim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207103 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: implement BFI optimisationTim Northover2014-04-24
| | | | | | | | | | | ARM64 was not producing pure BFI instructions for bitfield insertion operations, unlike AArch64. The approach had to be a little different (in ISelDAGToDAG rather than ISelLowering), and the outcomes aren't identical but hopefully this gives it similar power. This should address PR19424. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207102 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: port more testsTim Northover2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207101 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] Fix instrumentation of x86 intel syntax inline assembly.Evgeniy Stepanov2014-04-24
| | | | | | | | Patch by Yuri Gorshenin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207092 91177308-0d34-0410-b5e6-96231b3b80d8
* [CLNUP] Test commit. Remove newline.Zinovy Nis2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207089 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Emit test instead of constant shift + compare if the shift result is ↵Benjamin Kramer2014-04-24
| | | | | | | | | | | | | | | | | | unused. This allows us to compile return (mask & 0x8 ? a : b); into testb $8, %dil cmovnel %edx, %esi instead of andl $8, %edi shrl $3, %edi cmovnel %edx, %esi which we formed previously because dag combiner canonicalizes setcc of and into shift. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207088 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow vectorization of few missed llvm intrinsic calls in BBVectorizor by ↵Karthik Bhat2014-04-24
| | | | | | handling them in isVectorizableIntrinsic function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207085 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR18921, "vmov" part.Stepan Dyatkovskiy2014-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | Added support for bytes replication feature, so it could be GAS compatible. E.g. instructions below: "vmov.i32 d0, 0xffffffff" "vmvn.i32 d0, 0xabababab" "vmov.i32 d0, 0xabababab" "vmov.i16 d0, 0xabab" are incorrect, but we could deal with such cases. For first one we should emit: "vmov.i8 d0, 0xff" For second one ("vmvn"): "vmov.i8 d0, 0x54" For last two instructions it should emit: "vmov.i8 d0, 0xab" P.S.: In ARMAsmParser.cpp I have also fixed few nearby style issues in old code. Just for keeping method bodies in harmony with themselves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207080 91177308-0d34-0410-b5e6-96231b3b80d8
* [InstCombine][x86] Constant fold psll intrinsics.Michael J. Spencer2014-04-24
| | | | | | | | | | | | This excludes avx512 as I don't have hardware to verify. It excludes _dq variants because they are represented in the IR as <{2,4} x i64> when it's actually a byte shift of the entire i{128,265}. This also excludes _dq_bs as they aren't at all supported by the backend. There are also no corresponding instructions in the ISA. I have no idea why they exist... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207058 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize some special cases for SSE4a insertqiFilipe Cabecinhas2014-04-24
| | | | | | | | | | | | | | | | | | | | Summary: Since the upper 64 bits of the destination register are undefined when performing this operation, we can substitute it and let the optimizer figure out that only a copy is needed. Also added range merging, if an instruction copies a range that can be merged with a previous copied range. Added test cases for both optimizations. Reviewers: grosbach, nadav CC: llvm-commits Differential Revision: http://reviews.llvm.org/D3357 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207055 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle addrspacecast when looking at memcpys from globalsMatt Arsenault2014-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207054 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: disable test on thumbv7-windowsSaleem Abdulrasool2014-04-23
| | | | | | | This is dependent on changes that are not fully ready to be merged yet (WoA object file emission). The test can be re-enabled for that target later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207038 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-cov: Add support for gcov's --long-file-names optionJustin Bogner2014-04-23
| | | | | | | | GCOV provides an option to prepend output file names with the source file name, to disambiguate between covered data that's included from multiple sources. Add a flag to llvm-cov that does the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207035 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: move test from Generic to COFFSaleem Abdulrasool2014-04-23
| | | | | | This is a COFF specific test, move it to COFF to fix the Hexagon buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207030 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: move ARM64 test from AArch64 directorySaleem Abdulrasool2014-04-23
| | | | | | | The test was changed from aarch64 to arm64 but not moved. The test would fail if the backend was not built. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207029 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: honour IMAGE_SCN_CNT_INITIALIZED_DATASaleem Abdulrasool2014-04-23
| | | | | | | Emit the flag to indicate to the assembler that a section contains data if there is pre-populated data present. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207028 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Fix the information we give to the peephole optimizer for comparison.Quentin Colombet2014-04-23
| | | | | | | | | | ANDS does not use the same encoding scheme as other xxxS instructions (e.g., ADDS). Take that into account to avoid wrong peephole optimization. <rdar://problem/16693089> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207020 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add a test that used to be broken that I forgot to addMatt Arsenault2014-04-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207017 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert test to FileCheckMatt Arsenault2014-04-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207015 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark llvm/test/BugPoint/compile-custom.ll as XFAIL:vg_leak.NAKAMURA Takumi2014-04-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206989 91177308-0d34-0410-b5e6-96231b3b80d8
* Create MCTargetOptions.Evgeniy Stepanov2014-04-23
| | | | | | | | | | For now it contains a single flag, SanitizeAddress, which enables AddressSanitizer instrumentation of inline assembly. Patch by Yuri Gorshenin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206971 91177308-0d34-0410-b5e6-96231b3b80d8
* [LV] Statistics numbers for LoopVectorize introduced: a number of analyzed ↵Alexander Musman2014-04-23
| | | | | | | | | | | | | loops & a number of vectorized loops. Use -stats to see how many loops were analyzed for possible vectorization and how many of them were actually vectorized. Patch by Zinovy Nis Differential Revision: http://reviews.llvm.org/D3438 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206956 91177308-0d34-0410-b5e6-96231b3b80d8
* X86Disassembler - fixed a bug in immediate printElena Demikhovsky2014-04-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206953 91177308-0d34-0410-b5e6-96231b3b80d8
* Integrated assbemler, macros: added 'vararg' argument qualifier support.Stepan Dyatkovskiy2014-04-23
| | | | | | | | Note, currently we have no 'vararg' support for darwin macros. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206951 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Enable feature predicates for NEON / FP / CRYPTO.Kevin Qin2014-04-23
| | | | | | | | AArch64 has feature predicates for NEON, FP and CRYPTO instructions. This allows the compiler to generate code without using FP, NEON or CRYPTO instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206949 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test/CodeGen/arm.llReid Kleckner2014-04-23
| | | | | | | The 'CHECK: add' line was occasionally matching against the filename, breaking the subsequent CHECK-NOT. Also use CHECK-LABEL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206936 91177308-0d34-0410-b5e6-96231b3b80d8
* Follow aliases when determining if a symbol is thumb.Rafael Espindola2014-04-22
| | | | | | This fixes pr19484. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206917 91177308-0d34-0410-b5e6-96231b3b80d8
* [Constant Hoisting] Materialize the constant before the cloned cast instruction.Juergen Ributzka2014-04-22
| | | | | | | | | | | | In the case where the constant comes from a cloned cast instruction, the materialization code has to go before the cloned cast instruction. This commit fixes the method that finds the materialization insertion point by making it aware of this case. This fixes <rdar://problem/15532441> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206913 91177308-0d34-0410-b5e6-96231b3b80d8
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