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* Teach DAGCombiner how to fold a SIGN_EXTEND_INREG of a BUILD_VECTOR ofAndrea Di Biagio2013-12-27
| | | | | | | | | | | | | | | | | | | | | | ConstantSDNodes (or UNDEFs) into a simple BUILD_VECTOR. For example, given the following sequence of dag nodes: i32 C = Constant<1> v4i32 V = BUILD_VECTOR C, C, C, C v4i32 Result = SIGN_EXTEND_INREG V, ValueType:v4i1 The SIGN_EXTEND_INREG node can be folded into a build_vector since the vector in input is a BUILD_VECTOR of constants. The optimized sequence is: i32 C = Constant<-1> v4i32 Result = BUILD_VECTOR C, C, C, C git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198084 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize armv7a and friends as aliases for armv7-a etc. for the purposeJoerg Sonnenberger2013-12-26
| | | | | | | of architecture naming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198043 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: support .even directiveSaleem Abdulrasool2013-12-26
| | | | | | | The .even directive aligns content to an evan-numbered address. This is an ARM specific directive applicable to any section. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198031 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.Venkatraman Govindaraju2013-12-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198030 91177308-0d34-0410-b5e6-96231b3b80d8
* [ASan] Fix the tests broken by r198018 to check for private linkage of ↵Alexander Potapenko2013-12-25
| | | | | | ASan-generated globals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198020 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips] Does not take in account 'use-soft-float' attribute's value whenSimon Atanasyan2013-12-25
| | | | | | | | consider to generate stubs for mips16 hard-float mode. The patch reviewed by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198019 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky2013-12-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198013 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS load effective address.Zoran Jovanovic2013-12-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198010 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS FPU instructions 2.Zoran Jovanovic2013-12-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198009 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Fix a problem that the register order of fmls/fmla by element is ↵Hao Liu2013-12-25
| | | | | | | | | | | | incorrect. E.g. the codegen result is fmls v1.2s, v0.2s, v2.s[3] which is expected to be fmls v0.2s, v1.2s, v2.s[3] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198001 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing pattern matches to support ACLE intrinsics of AArch64 NEON.Jiangning Liu2013-12-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197993 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-symbolizer: add --obj flag to specify a single object file that should ↵Alexey Samsonov2013-12-24
| | | | | | be symbolized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197988 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use interlocked-access 1 instructions for CodeGenRichard Sandiford2013-12-24
| | | | | | | | | | ...namely LOAD AND ADD, LOAD AND AND, LOAD AND OR and LOAD AND EXCLUSIVE OR. LOAD AND ADD LOGICAL isn't really separately useful for LLVM. I'll look at adding reusing the CC results in new year. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197985 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add MC support for interlocked-access 1 instructionsRichard Sandiford2013-12-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197984 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: fixed some patterns for MVT::i1Elena Demikhovsky2013-12-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197981 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Add patterns to match normal shift nodes: shl, sra and srl.Hao Liu2013-12-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197969 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fix a bug when lowering BUILD_VECTOR.Kevin Qin2013-12-24
| | | | | | | | | DAG.getVectorShuffle() doesn't always return a vector_shuffle node. If mask is the exact sequence of it's operand(For example, operand_0 is v8i8, and the mask is 0, 1, 2, 3, 4, 5, 6, 7), it will directly return that operand. So a check is added here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197967 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fix a pattern match failure with NEON_VDUP.Kevin Qin2013-12-24
| | | | | | | | This failure caused by improper condition when lowering shuffle_vector to scalar_to_vector. After this patch NEON_VDUP with v1i64 will not be generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197966 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Check fmul node single use in fused multiply patternsAna Pazos2013-12-24
| | | | | | | | | | | | Check for single use of fmul node in fused multiply patterns to allow generation of fused multiply add/sub instructions. Otherwise fmul operation ends up being repeated more than once which does not help peformance on targets with only one MAC unit, as for example cortex-a53. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197929 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fixed fused multiply negate add/sub patternsAna Pazos2013-12-24
| | | | | | | | | | | | | | | | | | | | The correct pattern matching should be: - fnmadd is (-Ra) + (-Rn)*Rm which should be matched as: fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra) and as (f32 (fsub (f32 (fneg FPR32:$Ra)), (f32 (fmul FPR32:$Rn, FPR32:$Rm)))) - fnmsub is (-Ra) + Rn*Rm which should be matched as fma node:$Rn, node:$Rm, (fneg node:$Ra) and as (f32 (fsub (f32 (fmul FPR32:$Rn, FPR32:$Rm)), FPR32:$Ra)))) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197928 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug info: Add enumerators to the __apple_names accelerator table.Adrian Prantl2013-12-23
| | | | | | rdar://problem/11516681. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197927 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to indvars for optimizing sadd.with.overflow.Andrew Trick2013-12-23
| | | | | | | | | | | | | | | | Split sadd.with.overflow into add + sadd.with.overflow to allow analysis and optimization. This should ideally be done after InstCombine, which can perform code motion (eventually indvars should run after all canonical instcombines). We want ISEL to recombine the add and the check, at least on x86. This is currently under an option for reducing live induction variables: -liv-reduce. The next step is reducing liveness of IVs that are live out of the overflow check paths. Once the related optimizations are fully developed, reviewed and tested, I do expect this to become default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197926 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug info: On ARM ensure that the data sections come before theAdrian Prantl2013-12-23
| | | | | | | | | (optional) DWARF sections, so compiling with -g does not result in different code being generated. rdar://problem/15623193 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197922 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: bkpt has an implicit immediate constant 0Saleem Abdulrasool2013-12-23
| | | | | | | | | | The bkpt mnemonic has an implicit immediate constant of 0 unless otherwise specified. Add an instruction alias for the unvalued breakpoint mnemonic to treat it as a 0. This improves compatibility with GNU AS. Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197913 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Scalarizer insertion point when replacing PHIs with insertelementsRichard Sandiford2013-12-23
| | | | | | | | | | | If the Scalarizer scalarized a vector PHI but could not scalarize all uses of it, it would insert a series of insertelements to reconstruct the vector PHI value from the scalar ones. The problem was that it would emit these insertelements immediately after the PHI, even if there were other PHIs after it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197909 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Scalarizer handling of vector GEPs with multiple index operandsRichard Sandiford2013-12-23
| | | | | | | The old code only worked for one index operand. Also handle "inbounds". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197908 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] don't unpoison redzones on function exit in use-after-return mode.Kostya Serebryany2013-12-23
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Before this change the instrumented code before Ret instructions looked like: <Unpoison Frame Redzones> if (Frame != OriginalFrame) // I.e. Frame is fake <Poison Complete Frame> Now the instrumented code looks like: if (Frame != OriginalFrame) // I.e. Frame is fake <Poison Complete Frame> else <Unpoison Frame Redzones> Reviewers: eugenis Reviewed By: eugenis CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2458 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197907 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]The compare to zero intrinsics should be implemented by 'icmp/fcmp' ↵Hao Liu2013-12-23
| | | | | | and 'sext' not 'zext'. Modify the test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197897 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX512: SETCC returns i1 for AVX-512 and i8 for all othersElena Demikhovsky2013-12-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197876 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure bitcode encoding of calling conventions stays stable. Patch by Boaz ↵Michael Kuperstein2013-12-22
| | | | | | Ouriel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197873 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheckize r197869Alp Toker2013-12-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197872 91177308-0d34-0410-b5e6-96231b3b80d8
* Relax tab check into a whitespace check to fix the test in r197869Alp Toker2013-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197870 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Generate valid identifiers for anonymous recordsAlp Toker2013-12-21
| | | | | | | | | | Backends like OptParserEmitter assume that record names can be used as valid identifiers. The period '.' in generated anonymous names broke that assumption, causing a build-time error and in practice forcing all records to be named. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197869 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the .secidx test I've forgotten to svn add in 197826Timur Iskhodzhanov2013-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197828 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement initial-exec TLS for PPC32.Roman Divacky2013-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197824 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS FPU instructions 1.Zoran Jovanovic2013-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197815 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Optimize comparisons with truncated extended loadsRichard Sandiford2013-12-20
| | | | | | | | | | | | | If the extension of a loaded value is compared against zero and used in other arithmetic, InstCombine will change the comparison to use the unextended load. It's also possible that the comparison could be against the unextended load from the outset. In DAG form this becomes a truncation of an extending load. We want to strip the truncation if possible so that we can use load-and-test instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197804 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Extend RISBG optimizationRichard Sandiford2013-12-20
| | | | | | | | | | | | | | The handling of ANY_EXTEND and ZERO_EXTEND was too strict. In this context we can treat ZERO_EXTEND in much the same way as an AND and then also handle outermost ZERO_EXTENDs. I couldn't find a test that benefited from the ANY_EXTEND change, but it's more obvious to write it this way once SIGN_EXTEND and ZERO_EXTEND are handled differently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197802 91177308-0d34-0410-b5e6-96231b3b80d8
* Transforms: Don't create bad weights when eliminating dead casesJustin Bogner2013-12-20
| | | | | | | | | If we happen to eliminate every case in a switch that has branch weights, we currently try to create metadata for the one remaining branch, triggering an assert. Instead, we need to check that the metadata we're trying to create is sensible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197791 91177308-0d34-0410-b5e6-96231b3b80d8
* test: Make a branchweight test more specificJustin Bogner2013-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197790 91177308-0d34-0410-b5e6-96231b3b80d8
* test: Prefer CHECK-LABEL to CHECK in branchweight testsJustin Bogner2013-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197789 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: add support for the .pool directiveSaleem Abdulrasool2013-12-20
| | | | | | | The .pool directive is an alias for the .ltorg directive used to create a literal pool. Simply treat .pool as if .ltorg was passed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197787 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Allow ftruncTom Stellard2013-12-20
| | | | | | | | | | | | v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc v3: move ftrunc pattern next to TRUNC definition, it's available since R600 Patch By: Jan Vesely Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197783 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove extra check line that's failing on windows and not necessary atEric Christopher2013-12-20
| | | | | | the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197782 91177308-0d34-0410-b5e6-96231b3b80d8
* This test requires object emission.Eric Christopher2013-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197781 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for a CU to output a set of ranges for the CU. This is usefulEric Christopher2013-12-20
| | | | | | | | when you want to have the full list of addresses for a particular CU or when you have multiple modules linked together and can't depend upon the ordering of a single CU for begin/end ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197776 91177308-0d34-0410-b5e6-96231b3b80d8
* move test back into the parent directory and add a REQUIRES: obj emission.Adrian Prantl2013-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197759 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the ML test to expect the new string format of getStringRepresentation.Rafael Espindola2013-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197750 91177308-0d34-0410-b5e6-96231b3b80d8
* Un-revert: the buildbot failure in LLVM on lld-x86_64-win7 had me withKevin Enderby2013-12-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this commit as the only one on the Blamelist so I quickly reverted this. However it was actually Nick's change who has since fixed that issue. Original commit message: Changed the X86 assembler for intel syntax to work with directional labels. The X86 assembler as a separate code to parser the intel assembly syntax in X86AsmParser::ParseIntelOperand(). This did not parse directional labels. And if something like 1f was used as a branch target it would get an "Unexpected token" error. The fix starts in X86AsmParser::ParseIntelExpression() in the case for AsmToken::Integer, it needs to grab the IntVal from the current token then look for a 'b' or 'f' following an Integer. Then it basically needs to do what is done in AsmParser::parsePrimaryExpr() for directional labels. It saves the MCExpr it creates in the IntelExprStateMachine in the Sym field. When it returns to X86AsmParser::ParseIntelOperand() it looks for a non-zero Sym field in the IntelExprStateMachine and if set it creates a memory operand not an immediate operand it would normally do for the Integer. rdar://14961158 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197744 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert my change to the X86 assembler for intel syntax to work withKevin Enderby2013-12-19
| | | | | | | directional labels. Because it doesn't work for windows :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197731 91177308-0d34-0410-b5e6-96231b3b80d8
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