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* Add AArch64 as an experimental target.Tim Northover2013-01-31
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
* Made the min-trip-count-switch test X86-specific to avoidPekka Jaaskelainen2013-01-31
| | | | | | | breakage with builds without X86-support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174052 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r173946. This breaks compilation of googletest with ClangAlexey Samsonov2013-01-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174048 91177308-0d34-0410-b5e6-96231b3b80d8
* Filecheckized 2x tests in SimplifyCFG and removed their date prefix to fit ↵Michael Gottesman2013-01-31
| | | | | | with current llvm style for test names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174011 91177308-0d34-0410-b5e6-96231b3b80d8
* Check and allow floating point registers to select the size of theEric Christopher2013-01-31
| | | | | | | register for inline asm. This conforms to how gcc allows for effective casting of inputs into gprs (fprs is already handled). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174008 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace some more greps with FileChecks in testsEli Bendersky2013-01-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174006 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite this test properly with a FileCheck instead of grepsEli Bendersky2013-01-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173997 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ConstantFold's folding of icmp instructions to recognize that,Dan Gohman2013-01-31
| | | | | | | | for example, a one-past-the-end pointer from one global variable may be equal to the base pointer of another global variable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173995 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC QPX requires a 32-byte aligned stackHal Finkel2013-01-30
| | | | | | | On systems which support the QPX vector instructions, the stack must be 32-byte aligned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173993 91177308-0d34-0410-b5e6-96231b3b80d8
* Forgot the test case before.Evan Cheng2013-01-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173988 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions for the PPC a2q core marked as having QPX availableHal Finkel2013-01-30
| | | | | | | | This is the first commit of a large series which will add support for the QPX vector instruction set to the PowerPC backend. This instruction set is used on the IBM Blue Gene/Q supercomputers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173973 91177308-0d34-0410-b5e6-96231b3b80d8
* Linker: correctly link in dbg.declareManman Ren2013-01-30
| | | | | | | | | | | | | | | | | Given source IR: call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !14), !dbg !15 we used to generate call void @llvm.dbg.declare(metadata !27, metadata !28), !dbg !29 !27 = metadata !{null} With this patch, we will correctly generate call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !27), !dbg !28 Looking up %argc.addr in ValueMap will return null, since %argc.addr is already correctly set up, we can use identity mapping. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173946 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-30
| | | | | | | | | | More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing header and test cases for r173939.Logan Chien2013-01-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173941 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: canonicalize sext-and --> selectNadav Rotem2013-01-30
| | | | | | | | | | sext-not-and --> select. Patch by Muhammad Tauqir Ahmad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173901 91177308-0d34-0410-b5e6-96231b3b80d8
* build: add --with-python optionSaleem Abdulrasool2013-01-30
| | | | | | | | | | | | This adds a new --with-python option to allow configuration of the python binary for building. If not specified, $PATH will be searched for common python binary names (python, python2, python3). If specified, and the path is not executable, it will attempt to search $PATH. Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> Reviewed-by: Eric Christopher <echristo@gmail.com>, Daniel Dunbar <daniel@zuster.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173890 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements runtime ARM specificJack Carter2013-01-30
| | | | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173885 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements runtime Mips specificJack Carter2013-01-30
| | | | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173884 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch reworks how llvm targets set Jack Carter2013-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | and update ELF header e_flags. Currently gathering information such as symbol, section and data is done by collecting it in an MCAssembler object. From MCAssembler and MCAsmLayout objects ELFObjectWriter::WriteObject() forms and streams out the ELF object file. This patch just adds a few members to the MCAssember class to store and access the e_flag settings. It allows for runtime additions to the e_flag by assembler directives. The standalone assembler can get to MCAssembler from getParser().getStreamer().getAssembler(). This patch is the generic infrastructure and will be followed by patches for ARM and Mips for their target specific use. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173882 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Test case for r173862.Akira Hatanaka2013-01-30
| | | | | | | Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173863 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding simple cast cost to ARMRenato Golin2013-01-29
| | | | | | | | | | | Changing ARMBaseTargetMachine to return ARMTargetLowering intead of the generic one (similar to x86 code). Tests showing which instructions were added to cast when necessary or cost zero when not. Downcast to 16 bits are not lowered in NEON, so costs are not there yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173849 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC][COFF] Delay handling symbol aliases when writingMichael J. Spencer2013-01-29
| | | | | | Fixes PR14447 and PR9034. Patch by Nico Rieck! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173839 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorize: convert TinyTripCountVectorThreshold constantPekka Jaaskelainen2013-01-29
| | | | | | | | to a command line switch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173837 91177308-0d34-0410-b5e6-96231b3b80d8
* Support artificial parameters in function types.David Blaikie2013-01-29
| | | | | | | Provides the functionality for Clang change r172911 - I just had this still lying around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173820 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 64-bit atomic operations in Thumb mode.Tim Northover2013-01-29
| | | | | | | | The ARM and Thumb variants of LDREXD and STREXD have different constraints and take different operands. Previously the code expanding atomic operations didn't take this into account and asserted in Thumb mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173780 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge SSE and AVX shuffle instructions in the comment printer.Craig Topper2013-01-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173777 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert getAttributes() to return an AttributeSetNode.Bill Wendling2013-01-29
| | | | | | | | The AttributeSetNode contains all of the attributes. This removes one (hopefully last) use of the Attribute class as a container of multiple attributes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173761 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for source and line information to IntelJITEventListener for ↵Andrew Kaylor2013-01-28
| | | | | | object emitted by MCJIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173712 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch addresses bug 15031.Bill Schmidt2013-01-28
| | | | | | | | | | | | | | | | | | | | | | | The common code in the post-RA scheduler to break anti-dependencies on the critical path contained a flaw. In the reported case, an anti-dependency between the overlapping registers %X4 and %R4 exists: %X29<def> = OR8 %X4, %X4 %R4<def>, %X3<def,dead,tied3> = LBZU 1, %X3<kill,tied1> The unpatched code breaks the dependency by replacing %R4 and its uses with %R3, the first register on the available list. However, %R3 and %X3 overlap, so this creates two overlapping definitions on the same instruction. The fix is straightforward, preventing selection of a register that overlaps any other defined register on the same instruction. The test case is reduced from the bug report, and verifies that we no longer produce "lbzu 3, 1(3)" when breaking this anti-dependency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173706 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Mostly disable msan-handle-icmp-exact.Evgeniy Stepanov2013-01-28
| | | | | | | | | It is way too slow. Change the default option value to 0. Always do exact shadow propagation for unsigned ICmp with constants, it is cheap (under 1% cpu time) and required for correctness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173682 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 256-bit PALIGNR comment decoding to understand that it works on ↵Craig Topper2013-01-28
| | | | | | independent 256-bit lanes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173674 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing l2rus instructions.Richard Osborne2013-01-27
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing l2r instructions.Richard Osborne2013-01-27
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing 1r instructions.Richard Osborne2013-01-27
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing 0r instructions.Richard Osborne2013-01-27
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
* When the legalizer is splitting vector shifts, the result may not have the ↵Benjamin Kramer2013-01-27
| | | | | | | | | | | | | | | right shift amount type. Fix that by adding a cast to the shift expander. This came up with vector shifts on sse-less X86 CPUs. <2 x i64> = shl <2 x i64> <2 x i64> -> i64,i64 = shl i64 i64; shl i64 i64 -> i32,i32,i32,i32 = shl_parts i32 i32 i64; shl_parts i32 i32 i64 Now we cast the last two i64s to the right type. Fixes the crash in PR14668. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173615 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-revert r173342, without losing the compile time improvements, flatChandler Carruth2013-01-27
| | | | | | out bug fixes, or functionality preserving refactorings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173610 91177308-0d34-0410-b5e6-96231b3b80d8
* PR14566: Debug Info: Removing top level lexical blocksDavid Blaikie2013-01-26
| | | | | | | | | | This adds support for LLVM to accept metadata that doesn't include a top level lexical block in a function. Specifically LLVM couldn't handle this when there were file changes relating to these blocks. I've updated a few test cases to ensure other functionality (such as inlining) isn't affected by this change, but haven't pervasively updated all the test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173592 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Decode PALIGN operands so I don't have to do it in my head.Benjamin Kramer2013-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173572 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Do splat promotion later, so the optimizer can chew on it first.Benjamin Kramer2013-01-26
| | | | | | | | | | | | This catches many cases where we can emit a more efficient shuffle for a specific mask or when the mask contains undefs. Once the splat is lowered to unpacks we can't do that anymore. There is a possibility of moving the promotion after pshufb matching, but I'm not sure if pshufb with a mask loaded from memory is faster than 3 shuffles, so I avoided that for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173569 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheckize and merge some tests.Benjamin Kramer2013-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173568 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DIContext::getLineInfoForAddressRange() function and test. This ↵Andrew Kaylor2013-01-26
| | | | | | function allows a caller to obtain a table of line information for a function using the function's address and size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173537 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CMakeLists.txt: Add a dependency to llvm-rtdyld in check-llvm.NAKAMURA Takumi2013-01-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173528 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial implementation of PPCTargetTransformInfoHal Finkel2013-01-25
| | | | | | | | | | This provides a place to add customized operation cost information and control some other target-specific IR-level transformations. The only non-trivial logic in this checkin assigns a higher cost to unaligned loads and stores (covered by the included test case). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173520 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for applying in-memory relocations to the .debug_line section ↵Andrew Kaylor2013-01-25
| | | | | | and, in the case of ELF files, using symbol addresses when available for relocations to the .debug_info section. Also extending the llvm-rtdyld tool to add the ability to dump line number information for testing purposes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173517 91177308-0d34-0410-b5e6-96231b3b80d8
* XFAIL close-stderr on win32Reid Kleckner2013-01-25
| | | | | | | | The test runner does not rewrite instances of /dev/null inside the quoted sh command. /dev/null does not exist, so opt will fail to open it, and return a non-zero exit code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173509 91177308-0d34-0410-b5e6-96231b3b80d8
* Set the +x bit on two batch scriptsReid Kleckner2013-01-25
| | | | | | | | Cygwin git-svn will faithfully forward the svn properties all the way down to the NTFS executable permission. Without the +x bit, tests using these scripts fail with "Access Denied". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173508 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck-ify some grep testsReid Kleckner2013-01-25
| | | | | | | | These tests in particular try to use escaped square brackets as an argument to grep, which is failing for me with native win32 python. It appears the backslash is being lost near the CreateProcess*() call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173506 91177308-0d34-0410-b5e6-96231b3b80d8
* In this patch, we teach X86_64TargetMachine that it has a ILP32Eli Bendersky2013-01-25
| | | | | | | | | | | | | | | | | | | | | | | (defined by the x32 ABI) mode, in which case its pointers are 32-bits in size. This knowledge is also added to X86RegisterInfo that now returns the appropriate registers in getPointerRegClass. There are many outcomes to this change. In order to keep the patches separate and manageable, we start by focusing on some simple testable cases. The patch adds a test with passing a pointer to a function - focusing on the difference between the two data models for x86-64. Another test is added for handling of 'sret' arguments (and functionality is added in X86ISelLowering to make it work). A note on naming: the "x32 ABI" document refers to the AMD64 architecture (in LLVM it's distinguished by being is64Bits() in the x86 subtarget) with two variations: the LP64 (default) data model, and the ILP32 data model. This patch adds predicates to the subtarget which are consistent with this naming scheme. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173503 91177308-0d34-0410-b5e6-96231b3b80d8
* Add back a RUN line removed by mistake by a previous commitEli Bendersky2013-01-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173502 91177308-0d34-0410-b5e6-96231b3b80d8
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