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* DebugInfo: Tag units as having been indexed in GNU pubnames by using a ↵David Blaikie2014-03-06
| | | | | | | | | | DW_AT_GNU_pubnames of DW_FORM_flag(_present) rather than sec_offsets to the pubnames/types sections This is consistent with GDB ToT and reduces the number of relocations in (type and compile) units, substantially reducing relocations and debug size in fission + type units builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203082 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow constant folding of copysignKarthik Bhat2014-03-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203076 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Shrink pubnames/pubtypes in the presence of type units by only ↵David Blaikie2014-03-06
| | | | | | emitting pub sections for compile units git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203057 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixup PPC Darwin i1 argument handlingHal Finkel2014-03-06
| | | | | | | Like on other targets, we need to zero_extend/truncate i1 args before copying them to GPRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203045 91177308-0d34-0410-b5e6-96231b3b80d8
* When using CR bit registers on PPC32, handle the i1 vaarg caseHal Finkel2014-03-06
| | | | | | | | When copying an i1 value into a GPR for a vaarg call, we need to explicitly zero-extend the i1 value (otherwise an invalid CRBIT -> GPR copy will be generated). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203041 91177308-0d34-0410-b5e6-96231b3b80d8
* Change math intrinsic attributes from readonly to readnone. TheseRaul E. Silvera2014-03-06
| | | | | | | | | | are operations that do not access memory but may be sensitive to floating-point environment changes. LLVM does not attempt to model FP environment changes, so this was unnecessarily conservative and was getting on the way of some optimizations, in particular SLP vectorization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203037 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips] Testcase typo fix. No functionality change.Jack Carter2014-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203020 91177308-0d34-0410-b5e6-96231b3b80d8
* With PPC CR bit registers, handle int_to_fp on older coresHal Finkel2014-03-05
| | | | | | | | | On cores without fpcvt support, we cannot promote int_to_fp i1 operations, because there is nothing to promote them to. The most straightforward implementation of this uses a select to choose between the two possible resulting floating-point values (and that's what is done here). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203015 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix datalayout test that I broke with my previous LinkModules warning ↵JF Bastien2014-03-05
| | | | | | improvement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203011 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorizer: Preserve fast-math flagsArnold Schwaighofer2014-03-05
| | | | | | Fixes PR19045. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203008 91177308-0d34-0410-b5e6-96231b3b80d8
* Always print the implicit .text at the start of an asm file.Rafael Espindola2014-03-05
| | | | | | | | | | | | | | | | | Before llvm-mc would print it, but llc was assuming that it would produce another section changing directive before one was needed. That assumption is false with inline asm. Fixes PR19049. Another option would be to always create the section, but in the asm printer avoid printing sections changes during initialization. That would work, but * We do use the fact that llvm-mc prints it in testing. The tests can be changed if needed. * A quick poll on IRC suggest that most developers prefer the implicit .text to be printed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203001 91177308-0d34-0410-b5e6-96231b3b80d8
* ConstantFolding: Also fold the vector overloads of our math intrinsics.Benjamin Kramer2014-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202997 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower AVX v4i64->v4i32 truncate to one shuffle.Cameron McInally2014-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202996 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Correctly align arguments after a byval struct is passed on the stackOliver Stannard2014-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202985 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements .set dsp directive and sets appropriate feature ↵Vladimir Medic2014-03-05
| | | | | | bits.This directive is a counterpart of -mattr=dsp command line option with the exception that it does not influence elf header flags. The usage example is gives in test file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202966 91177308-0d34-0410-b5e6-96231b3b80d8
* Make stackmap machineinstrs clobber the scratch regs too.Andrew Trick2014-03-05
| | | | | | | | | | | | | Patchpoints already did this. Doing it for stackmaps is a convenience for the runtime in the event that it needs to scratch register to patch or perform a runtime call thunk. Unlike patchpoints, we just assume the AnyRegCC calling convention. This is the only language and target independent calling convention specific to stackmaps so makes sense. Although the calling convention is not currently used to select the scratch registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202943 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for dynamic allocas and inline asm that clobbers sp before buildingHans Wennborg2014-03-05
| | | | | | | | | | | | | | | | | | | selection dag (PR19012) In X86SelectionDagInfo::EmitTargetCodeForMemcpy we check with MachineFrameInfo to make sure that ESI isn't used as a base pointer register before we choose to emit rep movs (which clobbers esi). The problem is that MachineFrameInfo wouldn't know about dynamic allocas or inline asm that clobbers the stack pointer until SelectionDAGBuilder has encountered them. This patch fixes the problem by checking for such things when building the FunctionLoweringInfo. Differential Revision: http://llvm-reviews.chandlerc.com/D2954 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202930 91177308-0d34-0410-b5e6-96231b3b80d8
* Trivial test commit.Raul E. Silvera2014-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202924 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow constant folding of fma and fmuladdMatt Arsenault2014-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202914 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-objdump: Indent unwind info contents.Rui Ueyama2014-03-04
| | | | | | | | | | | Unwind info contents were indented at the same level as function table contents. That's a bit confusing because the unwind info is pointed by function table. In other places we usually increment indentation depth by one when dereferncing a pointer. This patch also removes extraneous newlines between function tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202879 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-objdump: Fix typo in output.Rui Ueyama2014-03-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202875 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Fix call of absolute address.Richard Osborne2014-03-04
| | | | | | | | | | | | | | | Previously for: tail call void inttoptr (i64 65536 to void ()*)() nounwind We would emit: bl 65536 The immediate operand of the bl instruction is a relative offset so it is wrong to use the absolute address here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202860 91177308-0d34-0410-b5e6-96231b3b80d8
* [CMake] check-llvm: Include "bugpoint" in dependent list.NAKAMURA Takumi2014-03-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202858 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Correct the behaviour of the COPY_FW pseudo on lanes 2 and 3.Daniel Sanders2014-03-04
| | | | | | | | | | Summary: Previously, attempting to extract lanes 2 and 3 would actually extract lane 1. The MSA CodeGen tests only covered lanes 0 and 1. Differential Revision: http://llvm-reviews.chandlerc.com/D2935 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202848 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements .set mips32r2 directive and sets appropriate feature ↵Vladimir Medic2014-03-04
| | | | | | bits. It also introduces helper functions that are used to set and clear feature bits as necessary. This directive is a counterpart of -mips32r2 command line options with the exception that it does not influence elf header flags. The usage example is gives in test file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202807 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-objdump: Print x64 unwind info in executable.Rui Ueyama2014-03-04
| | | | | | | | | | | | | | | | | | The original code does not work correctly on executable files because the code is written in such a way that only object files are assumed to be given to llvm-objdump. Contents of RuntimeFunction are different between executables and objects. In executables, fields in RuntimeFunction have actual addresses to unwind info structures. On the other hand, in object files, the fields have zero value, but instead there are relocations pointing to the fields, so that Linker will fill them at link-time. So, when we are reading an object file, we need to use relocation info to find the location of unwind info. When executable, we should just look at the values in RuntimeFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202785 91177308-0d34-0410-b5e6-96231b3b80d8
* Make a test for llvm-objdump a little bit more readable.Rui Ueyama2014-03-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202783 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Fix improper diagnostics about offset range of load/store instructions.Kevin Qin2014-03-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202775 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Fix Intel assembly parser for [global + offset]Reid Kleckner2014-03-04
| | | | | | | | | We were dropping the displacement on the floor if we also had some immediate offset. Should fix PR19033. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202774 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "[AArch64] This is a work in progress to provide a machine description"Chad Rosier2014-03-04
| | | | | | This reverts commit ff717c8fc786a0cfa1602982b91895fa09e514fc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202773 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] This is a work in progress to provide a machine descriptionChad Rosier2014-03-03
| | | | | | | | | | | | | | | | | | | for the Cortex-A53 subtarget in the AArch64 backend. This patch lays the ground work to annotate each AArch64 instruction (no NEON yet) with a list of SchedReadWrite types. The patch also provides the Cortex-A53 processor resources, maps those the the default SchedReadWrites, and provides basic latency. NEON support will be added in a subsequent patch with proper forwarding logic. Verification was done by setting the pre-RA scheduler to linearize to better gauge the effect of the MIScheduler. Even without modeling the forward logic, the results show a modest improvement for Cortex-A53. Reviewers: apazos, mcrosier, atrick Patch by Dave Estes <cestes@codeaurora.org>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202767 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass to emit DWARF path discriminators.Diego Novillo2014-03-03
| | | | | | | | | | | | | | | | DWARF discriminators are used to distinguish multiple control flow paths on the same source location. When this happens, instructions across basic block boundaries will share the same debug location. This pass detects this situation and creates a new lexical scope to one of the two instructions. This lexical scope is a child scope of the original and contains a new discriminator value. This discriminator is then picked up from MCObjectStreamer::EmitDwarfLocDirective to be written on the object file. This fixes http://llvm.org/bugs/show_bug.cgi?id=18270. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202752 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DWARF discriminator support to DILexicalBlocks.Diego Novillo2014-03-03
| | | | | | This adds support for emitting discriminators from DILexicalBlocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202736 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Prevent %lo relocation being used on MSA loads and stores.Daniel Sanders2014-03-03
| | | | | | | | | | | | | | | | | Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] support FK_Data_2 and FK_Data_8 to fix big-endian debug dataEd Maste2014-03-03
| | | | | | | | | | This fixes invalid lengths in .debug_aranges on big-endian mips64 (lengths appear to be left-shifted by 32 bits) and in .debug_loc. Differential Revision: http://llvm-reviews.chandlerc.com/D2517 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202716 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Handle X86 SIMD bitshift intrinsics.Evgeniy Stepanov2014-03-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202712 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements jalx instruction for Mips architecture.This ↵Vladimir Medic2014-03-03
| | | | | | instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202706 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmParser: add missed testsSaleem Abdulrasool2014-03-03
| | | | | | The diagnostics tests were missing from the previous introduction of ifeqs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202674 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc ↵Venkatraman Govindaraju2014-03-02
| | | | | | backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202670 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add return/rett instruction to Sparc backend.Venkatraman Govindaraju2014-03-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202666 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for decoding jmpl/retl/ret instruction.Venkatraman Govindaraju2014-03-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202663 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add fcmpe* instructions to Sparc backend.Venkatraman Govindaraju2014-03-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202661 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add VIS instructions to sparc backend.Venkatraman Govindaraju2014-03-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202660 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a PPC inline asm constraint type for single CR bitsHal Finkel2014-03-02
| | | | | | | | | | | | | | | | | Now that the PowerPC backend can track individual CR bits as first-class registers, we should also have a way of allocating them for inline asm statements. Because these registers are only one bit, if an output variable is implicitly cast to a larger integer size, we'll get an any_extend to that larger type (this is part of the existing target-independent logic). As a result, regardless of the size of the output type, only the first bit is meaningful. The constraint identifier "wc" has been chosen for this purpose. Although gcc does not currently support allocating individual CR bits, this identifier choice has been coordinated with the gcc PowerPC team, and will be marked as reserved for this purpose in the gcc constraints.md file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202657 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure bitcode encoding of instructions and their operands stays stable.Michael Kuperstein2014-03-02
| | | | | | | | | This includes instructions that relate to memory access (load/store/GEP), comparison instructions and calls. Work was done by lama.saba@intel.com. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202647 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9] Adds support for branch on integer register instructions (BPr) and ↵Venkatraman Govindaraju2014-03-02
| | | | | | conditional moves on integer register (MOVr/FMOVr). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202628 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Fixed extract_vector_elt for v8i1 vectorElena Demikhovsky2014-03-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202624 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing branches and conditional move instructions ↵Venkatraman Govindaraju2014-03-02
| | | | | | with %fcc1-%fcc3 conditional registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202616 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing fcmp with %fcc registers.Venkatraman Govindaraju2014-03-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202610 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9] Add support for parsing branch instructions with prediction.Venkatraman Govindaraju2014-03-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202602 91177308-0d34-0410-b5e6-96231b3b80d8
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