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* Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessorsDaniel Dunbar2011-03-19
| | | | | | to canonicalize IR", it broke a lot of things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127954 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IREvan Cheng2011-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to have single return block (at least getting there) for optimizations. This is general goodness but it would prevent some tailcall optimizations. One specific case is code like this: int f1(void); int f2(void); int f3(void); int f4(void); int f5(void); int f6(void); int foo(int x) { switch(x) { case 1: return f1(); case 2: return f2(); case 3: return f3(); case 4: return f4(); case 5: return f5(); case 6: return f6(); } } => LBB0_2: ## %sw.bb callq _f1 popq %rbp ret LBB0_3: ## %sw.bb1 callq _f2 popq %rbp ret LBB0_4: ## %sw.bb3 callq _f3 popq %rbp ret This patch teaches codegenprep to duplicate returns when the return value is a phi and where the phi operands are produced by tail calls followed by an unconditional branch: sw.bb7: ; preds = %entry %call8 = tail call i32 @f5() nounwind br label %return sw.bb9: ; preds = %entry %call10 = tail call i32 @f6() nounwind br label %return return: %retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ] ret i32 %retval.0 This allows codegen to generate better code like this: LBB0_2: ## %sw.bb jmp _f1 ## TAILCALL LBB0_3: ## %sw.bb1 jmp _f2 ## TAILCALL LBB0_4: ## %sw.bb3 jmp _f3 ## TAILCALL rdar://9147433 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127953 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for legalizing UINT_TO_FP of vectors on platforms which doNadav Rotem2011-03-19
| | | | | | | | | | not have native support for this operation (such as X86). The legalized code uses two vector INT_TO_FP operations and is faster than scalarizing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127951 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable test to unbreak Linux. Radar 9156771.Stuart Hastings2011-03-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127945 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r127940.Devang Patel2011-03-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127941 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed an assert by the ARM disassembler for LDRD_PRE/POST.Johnny Chen2011-03-19
| | | | | | | | | The relevant instruction table entries were changed sometime ago to no longer take <Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127935 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheckize a test.Andrew Trick2011-03-19
| | | | | | | (one-by-one until valgrind is happy) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127925 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to the ARM asm parser for the register-shifted-register forms of ↵Owen Anderson2011-03-18
| | | | | | basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
* Match a few more obvious patterns to revsh. rdar://9147637.Evan Cheng2011-03-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127913 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r127852; it's apparently causing an ICE on mingw.Eli Friedman2011-03-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127909 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Fix various codegen issuesJustin Holewinski2011-03-18
| | | | | | | | - Emit mad instead of mad.rn for shader model 1.0 - Emit explicit mov.u32 instructions for reading global variables - (most PTX instructions cannot take global variable immediates) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127895 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid creating canonical induction variables for non-native types.Andrew Trick2011-03-18
| | | | | | | | | For example, on 32-bit architecture, don't promote all uses of the IV to 64-bits just because one use is a 64-bit cast. Alternate implementation of the patch by Arnaud de Grandmaison. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127884 91177308-0d34-0410-b5e6-96231b3b80d8
* Support explicit argument forms for the X86 string instructions.Joerg Sonnenberger2011-03-18
| | | | | | | For now, only the default segments are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127875 91177308-0d34-0410-b5e6-96231b3b80d8
* ptx: fix parameter order that is reversedChe-Liang Chiou2011-03-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127874 91177308-0d34-0410-b5e6-96231b3b80d8
* ptx: add unconditional and conditional branchChe-Liang Chiou2011-03-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127873 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a target-specific branchless method for double-width relationalEli Friedman2011-03-18
| | | | | | | | | | | | | comparisons on x86. Essentially, the way this works is that SUB+SBB sets the relevant flags the same way a double-width CMP would. This is a substantial improvement over the generic lowering in LLVM. The output is also shorter than the gcc-generated output; I haven't done any detailed benchmarking, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127852 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck-ize and update test.Eli Friedman2011-03-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127845 91177308-0d34-0410-b5e6-96231b3b80d8
* The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.Johnny Chen2011-03-18
| | | | | | | Remove the offending logic and update the test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127843 91177308-0d34-0410-b5e6-96231b3b80d8
* Try to not lose variable's debug info during instcombine.Devang Patel2011-03-17
| | | | | | | | This is done by lowering dbg.declare intrinsic into dbg.value intrinsic. Radar 9143931. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127834 91177308-0d34-0410-b5e6-96231b3b80d8
* It used to be that t_addrmode_s4 was used for both:Johnny Chen2011-03-17
| | | | | | | | | | | | o A8.6.195 STR (register) -- Encoding T1 o A8.6.193 STR (immediate, Thumb) -- Encoding T1 It has been changed so that now they use different addressing modes and thus different MC representation (Operand Infos). Modify the disassembler to reflect the change, and add relevant tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127833 91177308-0d34-0410-b5e6-96231b3b80d8
* BuildUDIV: If the divisor is even we can simplify the fixup of the ↵Benjamin Kramer2011-03-17
| | | | | | | | | | | | | | | | | | | | | | | multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127829 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply: Add type output to llvm-dis annotations. Patch by Yuri!Stuart Hastings2011-03-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127824 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XCore intrinsic for setpsc.Richard Osborne2011-03-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127821 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Mach-O: Fix regression introduced in r126127, this assignment shouldn't haveDaniel Dunbar2011-03-17
| | | | | | been removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127812 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/h-registers-1.ll: Add explicit -mtriple=x86_64-linux. It ↵NAKAMURA Takumi2011-03-17
| | | | | | does not need to be checked on x86_64-win32 (aka Win64). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127800 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix handling of @IDNTPOFF relocations, they need to get STT_TLS.Joerg Sonnenberger2011-03-17
| | | | | | | While here, add VK_ARM_TPOFF and VK_ARM_GOTTPOFF, too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127780 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/constant-pool-remat-0.ll: FileCheck-ize and add explicit ↵NAKAMURA Takumi2011-03-16
| | | | | | -mtriple=x86_64-linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127775 91177308-0d34-0410-b5e6-96231b3b80d8
* The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byteCameron Zwarich2011-03-16
| | | | | | | | | | | rather than an int. Thankfully, this only causes LLVM to miss optimizations, not generate incorrect code. This just fixes the zext at the return. We still insert an i32 ZextAssert when reading a function's arguments, but it is followed by a truncate and another i8 ZextAssert so it is not optimized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127766 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename a test to be more inclusive.Cameron Zwarich2011-03-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127765 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r127757, "Patch to a fix dwarf relocation problem on ARM. One-line fixDaniel Dunbar2011-03-16
| | | | | | | plus the test where it used to break.", which broke Clang self-host of a Debug+Asserts compiler, on OS X. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127763 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XCore intrinsics for setclk, setrdy.Richard Osborne2011-03-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127761 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch to a fix dwarf relocation problem on ARM. One-line fix plus the test ↵Renato Golin2011-03-16
| | | | | | where it used to break. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127757 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test for i1 zeroext arguments on x86-64. We currently generate code thatCameron Zwarich2011-03-16
| | | | | | | conforms to the ABI, but DAGCombine could in theory recognize the sequence of zext asserts and truncates and generate incorrect code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127754 91177308-0d34-0410-b5e6-96231b3b80d8
* Add checkevent intrinsic to check if any resources owned by the current threadRichard Osborne2011-03-16
| | | | | | | can event. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127741 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86: FileCheck-ize and add actions for x86_64-linux and ↵NAKAMURA Takumi2011-03-16
| | | | | | x86_64-win32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127734 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86: Add a pattern for Win64.NAKAMURA Takumi2011-03-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127733 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86: FileCheck-ize and add explicit -mtriple=x86_64-linux. They ↵NAKAMURA Takumi2011-03-16
| | | | | | are useless to Win64 target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127732 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/byval*.ll: Win64 has not supported byval yet.NAKAMURA Takumi2011-03-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127731 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/dyn-stackalloc.ll: FileCheck-ize.NAKAMURA Takumi2011-03-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127730 91177308-0d34-0410-b5e6-96231b3b80d8
* Only convert allocas to scalars if it is profitable. The profitability metric ICameron Zwarich2011-03-16
| | | | | | | | | | | chose is having a non-memcpy/memset use and being larger than any native integer type. Originally I chose having an access of a size smaller than the total size of the alloca, but this caused some minor issues on the spirit benchmark where SRoA runs again after some inlining. This fixes <rdar://problem/8613163>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127718 91177308-0d34-0410-b5e6-96231b3b80d8
* Add native integer type TargetData to some existing tests.Cameron Zwarich2011-03-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127717 91177308-0d34-0410-b5e6-96231b3b80d8
* There were two issues fixed:Johnny Chen2011-03-15
| | | | | | | | | | | | | | | | | 1. The ARM Darwin *r9 call instructions were pseudo-ized recently. Modify the ARMDisassemblerCore.cpp file to accomodate the change. 2. The disassembler was unnecessarily adding 8 to the sign-extended imm24: imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate) // Encoding A1 It has no business doing such. Removed the offending logic. Add test cases to arm-tests.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127707 91177308-0d34-0410-b5e6-96231b3b80d8
* Some minor cleanups based on feedback.Bill Wendling2011-03-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127694 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587Evan Cheng2011-03-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127683 91177308-0d34-0410-b5e6-96231b3b80d8
* On the XCore the scavenging slot should be closest to the SP.Richard Osborne2011-03-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127680 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XCore intrinsics for getps, setps, setsr and clrsr.Richard Osborne2011-03-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127678 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Set PTX 2.0 as the minimum supported versionJustin Holewinski2011-03-15
| | | | | | | | - Remove PTX 1.4 code generation - Change type of intrinsics to .v4.i32 instead of .v4.i16 - Add and/or/xor integer instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127677 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not add PHIs with no users when creating LCSSA form. Patch by Andrew Clinton.Cameron Zwarich2011-03-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127674 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a peephole optimization to optimize pairs of bitcasts. e.g.Evan Cheng2011-03-15
| | | | | | | | | | | | | | | | | | | | | | | v2 = bitcast v1 ... v3 = bitcast v2 ... = v3 => v2 = bitcast v1 ... = v1 if v1 and v3 are of in the same register class. bitcast between i32 and fp (and others) are often not nops since they are in different register classes. These bitcast instructions are often left because they are in different basic blocks and cannot be eliminated by dag combine. rdar://9104514 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127668 91177308-0d34-0410-b5e6-96231b3b80d8
* PR9450: Make switch optimization in SimplifyCFG not dependent on the orderingEli Friedman2011-03-15
| | | | | | | | of pointers in an std::map. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127650 91177308-0d34-0410-b5e6-96231b3b80d8
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