summaryrefslogtreecommitdiff
path: root/utils
Commit message (Collapse)AuthorAge
* Remove unused field from FixedLenDecoderEmitter. Move NumberedInstructions ↵Craig Topper2012-03-13
| | | | | | declaration from class to run method since its only used there and was being reinitialized anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152616 91177308-0d34-0410-b5e6-96231b3b80d8
* lit: Pass %INCLUDE% to tests on Win32. clang may expect existence of ↵NAKAMURA Takumi2012-03-13
| | | | | | %INCLUDE% in vcvarsall.bat. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152588 91177308-0d34-0410-b5e6-96231b3b80d8
* DFAPacketizerEmitter: Prune includes.Benjamin Kramer2012-03-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152581 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more static tables of registers used by calling convention to ↵Craig Topper2012-03-11
| | | | | | uint16_t to reduce space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
* Shrink and reorder some fields in MCOperandInfo to fit it in 8 bytes to ↵Craig Topper2012-03-11
| | | | | | reduce size of static tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152524 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the x86 disassembler to at least print the lock prefix if it is the firstKevin Enderby2012-03-09
| | | | | | | | prefix. Added a FIXME to remind us this still does not work when it is not the first prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152414 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen/CodeEmitterGen.cpp: Fix an expression of generating bitmask.NAKAMURA Takumi2012-03-09
| | | | | | ~0U might be i32 on 32-bit hosts, then (uint64_t)~0U might not be expected as (i64)0xFFFFFFFF_FFFFFFFF, but as (i64)0x00000000_FFFFFFFF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152407 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-commit r152202 hopefully fixing the MSVC linker error.Craig Topper2012-03-08
| | | | | | | Original commit message: Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152296 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r152202 as it's causing internal buildbot failures.Chad Rosier2012-03-07
| | | | | | | | | | | Original commit message: Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152233 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to ↵Craig Topper2012-03-07
| | | | | | protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152202 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-06
| | | | | | Register pair, all lanes subscripting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-06
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix support for encodings up to 64-bits in length. TableGen was silently ↵Owen Anderson2012-03-06
| | | | | | truncating them to 32-bits prior to this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152148 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store indices into string table since C++ only allows 64K ↵Craig Topper2012-03-06
| | | | | | string literals so the index into the big string can never be larger than that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152105 91177308-0d34-0410-b5e6-96231b3b80d8
* Add asserts to ensure that values will fit into the tables.Craig Topper2012-03-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152104 91177308-0d34-0410-b5e6-96231b3b80d8
* Nuke a bit of dead code.Jim Grosbach2012-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152067 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-05
| | | | | | Use the new composite physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-05
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
* Shrink and reorder fields in MCRegisterClass to reduce size of static data.Craig Topper2012-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152019 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-05
| | | | | | static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper2012-03-04
| | | | | | static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-04
| | | | | | size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint8_t instead of enums to store values in X86 disassembler table. ↵Craig Topper2012-03-04
| | | | | | Shaves 150k off the size of X86DisassemblerDecoder.o git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151995 91177308-0d34-0410-b5e6-96231b3b80d8
* Perform the string table optimization for OperandMatchEntries too.Benjamin Kramer2012-03-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151986 91177308-0d34-0410-b5e6-96231b3b80d8
* Shrink the asm matcher tables.Benjamin Kramer2012-03-03
| | | | | | | | | | | | - Shrink the opcode field to 16 bits. - Shrink the AsmVariantID field to 8 bits. - Store the mnemonic string in a string table, store a 16 bit index. - Store a pascal-style length byte in the string instead of a null terminator, so we can avoid calling strlen on every entry we visit during mnemonic search. Shrinks X86AsmParser.o from 434k to 201k on x86_64 and eliminates relocs from the table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151984 91177308-0d34-0410-b5e6-96231b3b80d8
* StringToOffsetTable: Allow uniquing the first element, add an option to skip ↵Benjamin Kramer2012-03-03
| | | | | | appending a terminating null. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151983 91177308-0d34-0410-b5e6-96231b3b80d8
* Honour --config-prefix also for lit.local.cfg.Duncan Sands2012-03-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151977 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.Benjamin Kramer2012-03-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151821 91177308-0d34-0410-b5e6-96231b3b80d8
* Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.Jim Grosbach2012-03-01
| | | | | | | | Allows us to de-virtualize the function and provides access to it in the instruction printer, which is useful for handling composite physical registers (e.g., ARM register lists). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151815 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Emit the SubRegTable with the smallest possible integer type."Jim Grosbach2012-03-01
| | | | | | | | | | This reverts commit 151760. We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo, but to do that, the type of the lookup table needs to be the same for all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151814 91177308-0d34-0410-b5e6-96231b3b80d8
* Make TargetRegisterClasses non-virtual by making the only virtual function a ↵Benjamin Kramer2012-03-01
| | | | | | | | | | | function pointer. This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static initializer and a ton of cruft from the generated code. Shrinks ARMBaseRegisterInfo.o by ~100k. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151806 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit the "is an intrinsic overloaded" table as a bitfield.Benjamin Kramer2012-03-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151792 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit the intrinsic modref info as a lookup table instead of a huge switch.Benjamin Kramer2012-03-01
| | | | | | Shrinks BasicAliasAnalysis.o from 106k to 56k on i386. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151781 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement getSubRegIndex as a linear search on the SubRegTable instead of ↵Benjamin Kramer2012-02-29
| | | | | | | | | using a big switch. - The search bounds are constant, in the worst case (ARM target) it will scan over 30 uint16_ts. - This method isn't very hot, I had problems finding a testcase where it's called more than a dozen of times (no perf impact). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151773 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. 80 columns.Jim Grosbach2012-02-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151764 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit the SubRegTable with the smallest possible integer type.Benjamin Kramer2012-02-29
| | | | | | Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151760 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Spelling.Jim Grosbach2012-02-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151758 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the subregister indicies enum into the REGINFO_ENUM section.Jim Grosbach2012-02-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151756 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch TargetRegisterInfo::getSubReg() to use a lookup table.Jim Grosbach2012-02-29
| | | | | | | | | | Instead of nested switch statements, use a lookup table. On ARM, this replaces a 23k (x86_64 release build) function with a 16k table. Its not unlikely to be faster, as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151751 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert generated intrinsic attributes to use an array lookup as Chris ↵Craig Topper2012-02-28
| | | | | | suggested in PR11951. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151622 91177308-0d34-0410-b5e6-96231b3b80d8
* Update tblgen command guide. Remove unused tblgen InstrEnumEmitter files.Craig Topper2012-02-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151513 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-27
| | | | | | Kay Tiong Khoo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove 'if' from getSuperRegisters, getSubRegisters, and getOverlaps that ↵Craig Topper2012-02-23
| | | | | | were added in r151038. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151246 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove bad comma from .el file.Bill Wendling2012-02-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151189 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Foreach LoopDavid Greene2012-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some data structures to represent for loops. These will be referenced during object processing to do any needed iteration and instantiation. Add foreach keyword support to the lexer. Add a mode to indicate that we're parsing a foreach loop. This allows the value parser to early-out when processing the foreach value list. Add a routine to parse foreach iteration declarations. This is separate from ParseDeclaration because the type of the named value (the iterator) doesn't match the type of the initializer value (the value list). It also needs to add two values to the foreach record: the iterator and the value list. Add parsing support for foreach. Add the code to process foreach loops and create defs based on iterator values. Allow foreach loops to be matched at the top level. When parsing an IDValue check if it is a foreach loop iterator for one of the active loops. If so, return a VarInit for it. Add Emacs keyword support for foreach. Add VIM keyword support for foreach. Add tests to check foreach operation. Add TableGen documentation for foreach. Support foreach with multiple objects. Support non-braced foreach body with one object. Do not require types for the foreach declaration. Assume the iterator type from the iteration list element type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151164 91177308-0d34-0410-b5e6-96231b3b80d8
* Declare register classes as const. Fix a couple pointers to register classes ↵Craig Topper2012-02-22
| | | | | | that weren't already const. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151138 91177308-0d34-0410-b5e6-96231b3b80d8
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-22
| | | | | | to static data that should not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder some members in MCRegisterClass to remove padding on 64-bit builds.Craig Topper2012-02-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151043 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-06 06:27:05 +0000