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* Fix typoMichael Liao2012-09-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164012 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'virtual' keywoards to output file for overridden functions.Craig Topper2012-09-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164002 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'virtual' keywoards to output file for overridden functions.Craig Topper2012-09-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163999 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Doxygen issues: wrap code examples in \code and use \p to refer toDmitri Gribenko2012-09-15
| | | | | | | parameters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163984 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r163878 as it breaks on targets with alternate register names. Such ↵Craig Topper2012-09-15
| | | | | | targets do not exist in the main tree so this was not noticed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163959 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-15
| | | | | | Collect processor resources from the subtarget defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163953 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-15
| | | | | | Infer SchedClasses from variants defined by the target or subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163952 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-15
| | | | | | Collect SchedClasses and SchedRW types from the subtarget defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163951 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the second opcode info table to be 8, 16, or 32-bits as needed to ↵Craig Topper2012-09-14
| | | | | | represent additional fragments. This recovers some space on ATT X86 syntax and PowerPC which only need 40-bits instead of 48-bits. This also increases ARM to 64-bits to fully encode all of its operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163880 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce size of register name index tables by using uint16_t for all in tree ↵Craig Topper2012-09-14
| | | | | | targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163878 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmWriterEmitter: OpInfo2 should be unsigned 16-bit.Manman Ren2012-09-13
| | | | | | | Fix an issue in r163814. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163837 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmWriterEmitter: increase the number of bits for OpcodeInfo from 32-bit toManman Ren2012-09-13
| | | | | | | | | | | | 48-bit if necessary, in order to reduce the generated code size. We have 900 cases not covered by OpcodeInfo in ATT AsmWriter and more in Intel AsmWriter and ARM AsmWriter. This patch reduced the clang Release build size by 50k, running on a Mac Pro. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163814 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Doxygen issues:Dmitri Gribenko2012-09-13
| | | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163790 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-13
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163774 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Convert an assert() to a proper diagnostic.Jim Grosbach2012-09-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163726 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.Dmitri Gribenko2012-09-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163721 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve tblgen code cleanliness: create an unknown_class, from which the ↵Owen Anderson2012-09-11
| | | | | | unknown def inherits. Make tblgen check for that class, rather than checking for the def itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163664 91177308-0d34-0410-b5e6-96231b3b80d8
* Compute a map from register names to registers, rather than scanning the ↵Owen Anderson2012-09-11
| | | | | | list of registers every time we want to look up a register by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163659 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen2012-09-11
| | | | | | | | | | | | | | | | | Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean the sub-reg index composition maps at emission.Jakob Stoklund Olesen2012-09-11
| | | | | | | Preserve the Composites map in the CodeGenSubRegIndex class so it can be used to determine which sub-register indices can actually be composed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163629 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.Jakob Stoklund Olesen2012-09-11
| | | | | | | | Apparently, NumSubRegIndices was completely unused before. Adjust it by one to include the null subreg index, just like getNumRegs() includes the null register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163628 91177308-0d34-0410-b5e6-96231b3b80d8
* Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper2012-09-11
| | | | | | table size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163594 91177308-0d34-0410-b5e6-96231b3b80d8
* GTest on Android needs a custom tmpdir path.Evgeniy Stepanov2012-09-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163501 91177308-0d34-0410-b5e6-96231b3b80d8
* lit: Util.which(): Use os.path.isfile() instead of os.path.exists(), or it ↵NAKAMURA Takumi2012-09-08
| | | | | | | | hits to the directory. For example, which('loop-convert') returns 'loop-convert' when the directory 'loop-convert' exists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163469 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Add -exact-match option to FileCheck to allow clients to do exact ↵Ted Kremenek2012-09-08
| | | | | | | | | matches without using regular expressions." Turns out I did not need it after all. If we find a use for it in the future, we can resurrect it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163457 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactored DFA generator. Merged transition class into state class.Anshuman Dasgupta2012-09-07
| | | | | | | Patch by Ivan Llopard! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163424 91177308-0d34-0410-b5e6-96231b3b80d8
* Add -exact-match option to FileCheck to allow clients to do exact matches ↵Ted Kremenek2012-09-07
| | | | | | without using regular expressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163371 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-work bit/bits value resolving in tblgenMichael Liao2012-09-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - This patch is inspired by the failure of the following code snippet which is used to convert enumerable values into encoding bits to improve the readability of td files. class S<int s> { bits<2> V = !if(!eq(s, 8), {0, 0}, !if(!eq(s, 16), {0, 1}, !if(!eq(s, 32), {1, 0}, !if(!eq(s, 64), {1, 1}, {?, ?})))); } Later, PR8330 is found to report not exactly the same bug relevant issue to bit/bits values. - Instead of resolving bit/bits values separately through resolveBitReference(), this patch adds getBit() for all Inits and resolves bit value by resolving plus getting the specified bit. This unifies the resolving of bit with other values and removes redundant logic for resolving bit only. In addition, BitsInit::resolveReferences() is optimized to take advantage of this origanization by resolving VarBitInit's variable reference first and then getting bits from it. - The type interference in '!if' operator is revised to support possible combinations of int and bits/bit in MHS and RHS. - As there may be illegal assignments from integer value to bit, says assign 2 to a bit, but we only check this during instantiation in some cases, e.g. bit V = !if(!eq(x, 17), 0, 2); Verbose diagnostic message is generated when invalid value is resolveed to help locating the error. - PR8330 is fixed as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163360 91177308-0d34-0410-b5e6-96231b3b80d8
* Tablegen: Add OperandWithDefaultOps Operand typeTom Stellard2012-09-06
| | | | | | | This Operand type takes a default argument, and is initialized to this value if it does not appear in a patter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163315 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-06
| | | | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
* Constify subtarget info properly so that we dont cast away the const inRoman Divacky2012-09-05
| | | | | | | the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163251 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix function name per coding standard.Chad Rosier2012-09-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163187 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix function name per coding standard.Chad Rosier2012-09-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163186 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Remove the Inline Asm Non-Standard Dialect attribute. ThisChad Rosier2012-09-04
| | | | | | | implementation does not co-exist well with how the sideeffect and alignstack attributes are handled. The reverts r161641. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163174 91177308-0d34-0410-b5e6-96231b3b80d8
* [LIT] Add a clang_tools_extra_site_cfg to match the various other site_cfg.David Blaikie2012-09-04
| | | | | | | | | This doesn't seem ideal, perhaps we could just keep the llvm_site_cfg and have other config (clang and clang-tools-extra) derive their site_cfg from that. Suggestions/complaints/ideas welcome. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163171 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Android build of gtest and lib/Support.Evgeniy Stepanov2012-09-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163131 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Make comment more verbose and add an assert.Chad Rosier2012-09-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163125 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, addChad Rosier2012-09-03
| | | | | | | | the NumMCOperands argument to the GetMCInstOperandNum() function that is set to the number of MCOperands this asm operand mapped to. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163124 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add an interface to the GetMCInstOperandNum() function in theChad Rosier2012-09-03
| | | | | | | MCTargetAsmParser class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163122 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove extraneous return.Chad Rosier2012-09-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163119 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Return the MCOperandNum instead of passing a reference.Chad Rosier2012-09-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163118 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed unused argument.Chad Rosier2012-09-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163104 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Expose the Kind and Opcode variables from theChad Rosier2012-09-03
| | | | | | | | | | | MatchInstructionImpl() function. These values are used by the ConvertToMCInst() function to index into the ConversionTable. The values are also needed to call the GetMCInstOperandNum() function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163101 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an unused argument. The MCInst opcode is set in the ConvertToMCInst()Chad Rosier2012-08-31
| | | | | | | function nowadays. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163030 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for converting llvm.fma to fma4 instructions.Craig Topper2012-08-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162999 91177308-0d34-0410-b5e6-96231b3b80d8
* With the fix in r162954/162955 every cvt function returns true. Thus, haveChad Rosier2012-08-31
| | | | | | | | the ConvertToMCInst() return void, rather then a bool. Update all the cvt functions as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162961 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.Chad Rosier2012-08-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162946 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.Chad Rosier2012-08-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162945 91177308-0d34-0410-b5e6-96231b3b80d8
* Hoist a check to eliminate obvious mismatches as early as possible. Also, fixChad Rosier2012-08-30
| | | | | | | an 80-column violation in the generated code. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162944 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add a new function, GetMCInstOperandNum, to theChad Rosier2012-08-30
| | | | | | | | | | | | | | | | | | | | | | | | AsmMatcherEmitter. This function maps inline assembly operands to MCInst operands. For example, '__asm mov j, eax' is represented by the follow MCInst: <MCInst 1460 <MCOperand Reg:0> <MCOperand Imm:1> <MCOperand Reg:0> <MCOperand Expr:(j)> <MCOperand Reg:0> <MCOperand Reg:43>> The first 5 MCInst operands are a result of j matching as a memory operand consisting of a BaseReg (Reg:0), MemScale (Imm:1), MemIndexReg(Reg:0), Expr (Expr:(j), and a MemSegReg (Reg:0). The 6th MCInst operand represents the eax register (Reg:43). This translation is necessary to determine the Input and Output Exprs. If a single asm operand maps to multiple MCInst operands, the index of the first MCInst operand is returned. Ideally, it would return the operand we really care out (i.e., the Expr:(j) in this case), but I haven't found an easy way of doing this yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162920 91177308-0d34-0410-b5e6-96231b3b80d8
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