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* Add a wrapper for open.Rafael Espindola2013-07-16
| | | | | | | This centralizes the handling of O_BINARY and opens the way for hiding more differences (like how open behaves with directories). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186447 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch allows targets to define weather the instruction mnemonics in asm ↵Vladimir Medic2013-07-16
| | | | | | matcher tables will contain '.' character. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186388 91177308-0d34-0410-b5e6-96231b3b80d8
* Teaching llvm-tblgen to not emit a switch statement when there are no case ↵Aaron Ballman2013-07-15
| | | | | | statements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186330 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'const' qualifier to some arrays.Craig Topper2013-07-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186312 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-14
| | | | | | size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new directive called CHECK-LABEL to FileCheck.Stephen Lin2013-07-12
| | | | | | | | | CHECK-LABEL is meant to be used in place on CHECK on lines containing identifiers or other unique labels (they need not actually be labels in the source or output language, though.) This is used to break up the input stream into separate blocks delineated by CHECK-LABEL lines, each of which is checked independently. This greatly improves the accuracy of errors and fix-it hints in many cases, and allows for FileCheck to recover from errors in one block by continuing to subsequent blocks. Some tests will be converted to use this new directive in forthcoming patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186162 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.Charles Davis2013-07-12
| | | | | | | | | | | | | | | Summary: This patch adds explicit calling convention types for the Win64 and System V/x86-64 ABIs. This allows code to override the default, and use the Win64 convention on a target that wants to use SysV (and vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU attributes. Reviewers: CC: git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186144 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct comment.Duncan Sands2013-07-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185987 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend 'readonly' and 'readnone' to work on function arguments as well asNick Lewycky2013-07-06
| | | | | | | | functions. Make the function attributes pass add it to known library functions and when it can deduce it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185735 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a --crash option to not.Rafael Espindola2013-07-05
| | | | | | | | | | | | | Now the two possible uses of not are * not cmd Will return true if cmd doesn't crash and returns false. * not --crash cmd Will return true if cmd crashes. It will be used/tested in a followup commit for the clang crash recovery testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185678 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-04
| | | | | | specifying the vector size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve the compression of the tablegen DiffLists by introducing a new sortChad Rosier2013-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | algorithm when assigning EnumValues to the synthesized registers. The current algorithm, LessRecord, uses the StringRef compare_numeric function. This function compares strings, while handling embedded numbers. For example, the R600 backend registers are sorted as follows: T1 T1_W T1_X T1_XYZW T1_Y T1_Z T2 T2_W T2_X T2_XYZW T2_Y T2_Z In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2 have an EnumValue offset of 6 from one another. However, in other parts of the register bank, the scaling factors are different: dEnum/dN = 5: KC0_128_W KC0_128_X KC0_128_XYZW KC0_128_Y KC0_128_Z KC0_129_W KC0_129_X KC0_129_XYZW KC0_129_Y KC0_129_Z The diff lists do not work correctly because different kinds of registers have different 'scaling factors'. This new algorithm, LessRecordRegister, tries to enforce a scaling factor of 1. For example, the registers are now sorted as follows: T1 T2 T3 ... T0_W T1_W T2_W ... T0_X T1_X T2_X ... KC0_128_W KC0_129_W KC0_130_W ... For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I did see a few small regressions, but the differences were on the order of a few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even greater wins for targets with larger register files. Patch reviewed by Jakob. rdar://14006013 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185094 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Generate a function for getting operand indices based on their ↵Tom Stellard2013-06-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | defined names This patch modifies TableGen to generate a function in ${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used to look up indices for operands based on their names. In order to activate this feature for an instruction, you must set the UseNamedOperandTable bit. For example, if you have an instruction like: def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>; You can look up the operand indices using the new function, like this: Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0 Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1 Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2 The operand names are case sensitive, so $dst and $DST are considered different operands. This change is useful for R600 which has instructions with a large number of operands, many of which model single bit instruction configuration values. These configuration bits are common across most instructions, but may have a different operand index depending on the instruction type. It is useful to have a convenient way to look up the operand indices, so these bits can be generically set on any instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184879 91177308-0d34-0410-b5e6-96231b3b80d8
* keep only the StringRef version of getFileOrSTDIN.Rafael Espindola2013-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184826 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.Stefanus Du Toit2013-06-18
| | | | | | | | | | For decoding, keep the current behavior of always decoding these as their REP versions. In the future, this could be improved to recognize the cases where these behave as XACQUIRE and XRELEASE and decode them as such. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184207 91177308-0d34-0410-b5e6-96231b3b80d8
* Build Apple's llvmCore with --disable-zlib. <rdar://problem/14182316>Bob Wilson2013-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184164 91177308-0d34-0410-b5e6-96231b3b80d8
* Support BufferSize on ProcResGroup for unified MOp schedulers.Andrew Trick2013-06-15
| | | | | | And add Sandybridge/Haswell resource buffers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184034 91177308-0d34-0410-b5e6-96231b3b80d8
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-15
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use PathV1.h in FileUtilities.h.Rafael Espindola2013-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183941 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid using PathV1.h in Program.h.Rafael Espindola2013-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183940 91177308-0d34-0410-b5e6-96231b3b80d8
* Have sys::FindProgramByName return a std::string.Rafael Espindola2013-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183928 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the program class.Rafael Espindola2013-06-12
| | | | | | | It was only used to implement ExecuteAndWait and ExecuteNoWait. Expose just those two functions and make Execute and Wait implementations details. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183864 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen: Assert that InstRWs doesn't grows when we don't expect it.Benjamin Kramer2013-06-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183690 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen: always lookup values from the original vector as it could be grown ↵Benjamin Kramer2013-06-09
| | | | | | | | under our feet. PR16281. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183630 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a script to help us create source tar balls for the release.Bill Wendling2013-06-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183509 91177308-0d34-0410-b5e6-96231b3b80d8
* Use proper exit code.Bill Wendling2013-06-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183508 91177308-0d34-0410-b5e6-96231b3b80d8
* CodeGenSchedule: Use resize instead of copying a vectorArnold Schwaighofer2013-06-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183465 91177308-0d34-0410-b5e6-96231b3b80d8
* CodeGenSchedule: smallvector.push_back(smallvector[0]) is dangerousArnold Schwaighofer2013-06-06
| | | | | | | | | | The element passed to push_back is not copied before the vector reallocates. The client needs to copy the element first before passing it to push_back. No test case, will be tested by follow-up swift scheduler model change (it segfaults without this change). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183459 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unimplemented definition. Found using [-Wunused-member-function].Jakub Staszak2013-06-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183426 91177308-0d34-0410-b5e6-96231b3b80d8
* SubtargetEmitter fixArnold Schwaighofer2013-06-05
| | | | | | | | | Don't output data if we are supposed to ignore the record. Reapply of 183255, I don't think this was causing the tablegen segfault on linux testers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183311 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a tblgen subtargetemitter bug, for future Swift support.Andrew Trick2013-06-05
| | | | | | | | | | This fixes some of the ridiculously complex code for optimizing the machine model tables that are shared among all processors of a given target. A9 and Swift both use the "special" feature that maps old itinerary classes to new machine model defs. They map different overlapping subsets of instructions, which wasn't handled correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183302 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
* SubtargetEmitter fixArnold Schwaighofer2013-06-04
| | | | | | Don't output data if we are supposed to ignore the record. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183255 91177308-0d34-0410-b5e6-96231b3b80d8
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-31
| | | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha2013-05-31
| | | | | | | | | | | | | | | NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed bug when tests in executable partially used absolute paths.Galina Kistanova2013-05-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182910 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the MCRegAliasIterator tables and compute the aliases dynamically.Chad Rosier2013-05-28
| | | | | | | | | | | | | | | | | | | | | The size reduction in the RegDiffLists are rather dramatic. Here are a few size differences for MCTargetDesc.o files (before and after) in bytes: R600 - 36160B - 11184B - 69% reduction ARM - 28480B - 8368B - 71% reduction Mips - 816B - 576B - 29% reduction One side effect of dynamically computing the aliases is that the iterator does not guarantee that the entries are ordered or that duplicates have been removed. The documentation implies this is a safe assumption and I found no clients that requires these attributes (i.e., strict ordering and uniqueness). My local LNT tester results showed no execution-time failures or significant compile-time regressions (i.e., beyond what I would consider noise) for -O0g, -O2 and -O3 runs on x86_64 and i386 configurations. rdar://12906217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182783 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r182715 and r182758Alexey Samsonov2013-05-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182761 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixup for r182715: provide correct arg to --gtest-filterAlexey Samsonov2013-05-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182758 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed bug when tests in executable partially used absolute paths.Galina Kistanova2013-05-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182715 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize ValueType operands in source patterns for fast-isel.Bill Schmidt2013-05-22
| | | | | | | | | | | | | | | | | | | | | | Currently the fast-isel table generator recognizes registers, register classes, and immediates for source pattern operands. ValueType operands are not recognized. This is not a problem for existing targets with fast-isel support, but will not work for targets like PowerPC and SPARC that use types in source patterns. The proposed patch allows ValueType operands and treats them in the same manner as register classes. There is no convenient way to map from a ValueType to a register class, but there's no need to do so. The table generator already requires that all types in the source pattern be identical, and we know the register class of the output operand already. So we just assign that register class to any ValueType operands we encounter. No functional effect on existing targets. Testing deferred until the PowerPC target implements fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182512 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TargetRegisterInfo::getCoveringLanes().Jakob Stoklund Olesen2013-05-16
| | | | | | | | This lane mask provides information about which register lanes completely cover super-registers. See the block comment before getCoveringLanes(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182034 91177308-0d34-0410-b5e6-96231b3b80d8
* Use proper syntax.Bill Wendling2013-05-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181930 91177308-0d34-0410-b5e6-96231b3b80d8
* Add lldb and polly to the projects to tag.Bill Wendling2013-05-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181925 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'CHECK-DAG' supportMichael Liao2013-05-14
| | | | | | | | Refer to 'FileCheck.rst'f for details of 'CHECK-DAG'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181827 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor string checking. No functionality change.Michael Liao2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181824 91177308-0d34-0410-b5e6-96231b3b80d8
* Get the unittests compiling when building with cmake and the settingDuncan Sands2013-05-14
| | | | | | | -DLLVM_ENABLE_THREADS=false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181788 91177308-0d34-0410-b5e6-96231b3b80d8
* Add libcxx and clang-tools-extra to the testing thing.Bill Wendling2013-05-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181418 91177308-0d34-0410-b5e6-96231b3b80d8
* Add clang-tools-extra to the list of things to tag for the release.Bill Wendling2013-05-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181402 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the libc++ project to those we tag.Bill Wendling2013-05-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181371 91177308-0d34-0410-b5e6-96231b3b80d8
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