AArch64/ARM64: implement remaining TLS relocations (purely MC).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207668 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 34 insertions, 18 deletions

diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index 7572691fcf..764999b4e7 100644
--- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -3017,6 +3017,7 @@ bool ARM64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
                   .Case("dtprel_g1_nc", ARM64MCExpr::VK_DTPREL_G1_NC)
                   .Case("dtprel_g0", ARM64MCExpr::VK_DTPREL_G0)
                   .Case("dtprel_g0_nc", ARM64MCExpr::VK_DTPREL_G0_NC)
+                  .Case("dtprel_hi12", ARM64MCExpr::VK_DTPREL_HI12)
                   .Case("dtprel_lo12", ARM64MCExpr::VK_DTPREL_LO12)
                   .Case("dtprel_lo12_nc", ARM64MCExpr::VK_DTPREL_LO12_NC)
                   .Case("tprel_g2", ARM64MCExpr::VK_TPREL_G2)
@@ -3024,6 +3025,7 @@ bool ARM64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
                   .Case("tprel_g1_nc", ARM64MCExpr::VK_TPREL_G1_NC)
                   .Case("tprel_g0", ARM64MCExpr::VK_TPREL_G0)
                   .Case("tprel_g0_nc", ARM64MCExpr::VK_TPREL_G0_NC)
+                  .Case("tprel_hi12", ARM64MCExpr::VK_TPREL_HI12)
                   .Case("tprel_lo12", ARM64MCExpr::VK_TPREL_LO12)
                   .Case("tprel_lo12_nc", ARM64MCExpr::VK_TPREL_LO12_NC)
                   .Case("tlsdesc_lo12", ARM64MCExpr::VK_TLSDESC_LO12)
@@ -3522,7 +3524,9 @@ bool ARM64AsmParser::validateInstruction(MCInst &Inst,
     // and resolve the value and validate the result at fixup time, but
     // that's hard as we have long since lost any source information we
     // need to generate good diagnostics by that point.
-    if (Inst.getOpcode() == ARM64::ADDXri && Inst.getOperand(2).isExpr()) {
+    if ((Inst.getOpcode() == ARM64::ADDXri ||
+         Inst.getOpcode() == ARM64::ADDWri) &&
+        Inst.getOperand(2).isExpr()) {
       const MCExpr *Expr = Inst.getOperand(2).getExpr();
       ARM64MCExpr::VariantKind ELFRefKind;
       MCSymbolRefExpr::VariantKind DarwinRefKind;
@@ -3531,18 +3535,22 @@ bool ARM64AsmParser::validateInstruction(MCInst &Inst,
         return Error(Loc[2], "invalid immediate expression");
       }
 
-      if (DarwinRefKind == MCSymbolRefExpr::VK_PAGEOFF ||
-          DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGEOFF ||
-          ELFRefKind == ARM64MCExpr::VK_LO12 ||
+      // Note that we don't range-check the addend. It's adjusted modulo page
+      // size when converted, so there is no "out of range" condition when using
+      // @pageoff. Any validity checking for the value was done in the is*()
+      // predicate function.
+      if ((DarwinRefKind == MCSymbolRefExpr::VK_PAGEOFF ||
+           DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGEOFF) &&
+          Inst.getOpcode() == ARM64::ADDXri)
+        return false;
+      if (ELFRefKind == ARM64MCExpr::VK_LO12 ||
+          ELFRefKind == ARM64MCExpr::VK_DTPREL_HI12 ||
           ELFRefKind == ARM64MCExpr::VK_DTPREL_LO12 ||
           ELFRefKind == ARM64MCExpr::VK_DTPREL_LO12_NC ||
+          ELFRefKind == ARM64MCExpr::VK_TPREL_HI12 ||
           ELFRefKind == ARM64MCExpr::VK_TPREL_LO12 ||
           ELFRefKind == ARM64MCExpr::VK_TPREL_LO12_NC ||
           ELFRefKind == ARM64MCExpr::VK_TLSDESC_LO12) {
-        // Note that we don't range-check the addend. It's adjusted
-        // modulo page size when converted, so there is no "out of range"
-        // condition when using @pageoff. Any validity checking for the value
-        // was done in the is*() predicate function.
         return false;
       } else if (DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGEOFF) {
         // @gotpageoff can only be used directly, not with an addend.
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp
index b775dd332f..0990a701bc 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp
@@ -103,15 +103,19 @@ unsigned ARM64ELFObjectWriter::GetRelocType(const MCValue &Target,
     case FK_Data_8:
       return ELF::R_AARCH64_ABS64;
     case ARM64::fixup_arm64_add_imm12:
-      if (SymLoc == ARM64MCExpr::VK_DTPREL && IsNC)
+      if (RefKind == ARM64MCExpr::VK_DTPREL_HI12)
+        return ELF::R_AARCH64_TLSLD_ADD_DTPREL_HI12;
+      if (RefKind == ARM64MCExpr::VK_TPREL_HI12)
+        return ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12;
+      if (RefKind == ARM64MCExpr::VK_DTPREL_LO12_NC)
         return ELF::R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC;
-      if (SymLoc == ARM64MCExpr::VK_DTPREL && !IsNC)
+      if (RefKind == ARM64MCExpr::VK_DTPREL_LO12)
         return ELF::R_AARCH64_TLSLD_ADD_DTPREL_LO12;
-      if (SymLoc == ARM64MCExpr::VK_TPREL && IsNC)
+      if (RefKind == ARM64MCExpr::VK_TPREL_LO12_NC)
         return ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC;
-      if (SymLoc == ARM64MCExpr::VK_TPREL && !IsNC)
+      if (RefKind == ARM64MCExpr::VK_TPREL_LO12)
         return ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12;
-      if (SymLoc == ARM64MCExpr::VK_TLSDESC && IsNC)
+      if (RefKind == ARM64MCExpr::VK_TLSDESC_LO12)
         return ELF::R_AARCH64_TLSDESC_ADD_LO12_NC;
       if (SymLoc == ARM64MCExpr::VK_ABS && IsNC)
         return ELF::R_AARCH64_ADD_ABS_LO12_NC;
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
index be831b8cf0..3c6dbc85b1 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
@@ -288,7 +288,6 @@ ARM64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
     return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << 12));
   assert(MO.isExpr() && "Unable to encode MCOperand!");
   const MCExpr *Expr = MO.getExpr();
-  assert(ShiftVal == 0 && "shift not allowed on add/sub immediate with fixup");
 
   // Encode the 12 bits of the fixup.
   MCFixupKind Kind = MCFixupKind(ARM64::fixup_arm64_add_imm12);
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp
index c772002846..efa820b097 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp
@@ -49,6 +49,7 @@ StringRef ARM64MCExpr::getVariantKindName() const {
   case VK_DTPREL_G1_NC:        return ":dtprel_g1_nc:";
   case VK_DTPREL_G0:           return ":dtprel_g0:";
   case VK_DTPREL_G0_NC:        return ":dtprel_g0_nc:";
+  case VK_DTPREL_HI12:         return ":dtprel_hi12:";
   case VK_DTPREL_LO12:         return ":dtprel_lo12:";
   case VK_DTPREL_LO12_NC:      return ":dtprel_lo12_nc:";
   case VK_TPREL_G2:            return ":tprel_g2:";
@@ -56,6 +57,7 @@ StringRef ARM64MCExpr::getVariantKindName() const {
   case VK_TPREL_G1_NC:         return ":tprel_g1_nc:";
   case VK_TPREL_G0:            return ":tprel_g0:";
   case VK_TPREL_G0_NC:         return ":tprel_g0_nc:";
+  case VK_TPREL_HI12:          return ":tprel_hi12:";
   case VK_TPREL_LO12:          return ":tprel_lo12:";
   case VK_TPREL_LO12_NC:       return ":tprel_lo12_nc:";
   case VK_TLSDESC_LO12:        return ":tlsdesc_lo12:";
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h b/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h
index 5cce6ece9f..d832546517 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h
@@ -42,10 +42,11 @@ public:
     // MOVZ/MOVK.
     VK_PAGE     = 0x010,
     VK_PAGEOFF  = 0x020,
-    VK_G0       = 0x030,
-    VK_G1       = 0x040,
-    VK_G2       = 0x050,
-    VK_G3       = 0x060,
+    VK_HI12     = 0x030,
+    VK_G0       = 0x040,
+    VK_G1       = 0x050,
+    VK_G2       = 0x060,
+    VK_G3       = 0x070,
     VK_AddressFragBits = 0x0f0,
 
     // Whether the final relocation is a checked one (where a linker should
@@ -79,6 +80,7 @@ public:
     VK_DTPREL_G1_NC      = VK_DTPREL   | VK_G1      | VK_NC,
     VK_DTPREL_G0         = VK_DTPREL   | VK_G0,
     VK_DTPREL_G0_NC      = VK_DTPREL   | VK_G0      | VK_NC,
+    VK_DTPREL_HI12       = VK_DTPREL   | VK_HI12,
     VK_DTPREL_LO12       = VK_DTPREL   | VK_PAGEOFF,
     VK_DTPREL_LO12_NC    = VK_DTPREL   | VK_PAGEOFF | VK_NC,
     VK_GOTTPREL_PAGE     = VK_GOTTPREL | VK_PAGE,
@@ -90,6 +92,7 @@ public:
     VK_TPREL_G1_NC       = VK_TPREL    | VK_G1      | VK_NC,
     VK_TPREL_G0          = VK_TPREL    | VK_G0,
     VK_TPREL_G0_NC       = VK_TPREL    | VK_G0      | VK_NC,
+    VK_TPREL_HI12        = VK_TPREL    | VK_HI12,
     VK_TPREL_LO12        = VK_TPREL    | VK_PAGEOFF,
     VK_TPREL_LO12_NC     = VK_TPREL    | VK_PAGEOFF | VK_NC,
     VK_TLSDESC_LO12      = VK_TLSDESC  | VK_PAGEOFF | VK_NC,