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| author | Chad Rosier <mcrosier@codeaurora.org> | 2013-12-10 21:33:56 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2013-12-10 21:33:56 +0000 |
| commit | 2456ea5c926fca546a9e825526194516749b735c (patch) | |
| tree | 2bcf534e15a53dd497c80d68e399d1a94c7fcc86 /test/CodeGen | |
| parent | c000d11d5d853dc1c5a8a2468ce634e49009bc26 (diff) | |
| download | llvm-2456ea5c926fca546a9e825526194516749b735c.tar.gz llvm-2456ea5c926fca546a9e825526194516749b735c.tar.bz2 llvm-2456ea5c926fca546a9e825526194516749b735c.tar.xz | |
[AArch64] Refactor the NEON signed/unsigned floating-point convert to fixed-point
LLVM AArch64 intrinsics to use f32/f64, rather than their vector equivalents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196964 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/AArch64/neon-scalar-cvt.ll | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/test/CodeGen/AArch64/neon-scalar-cvt.ll b/test/CodeGen/AArch64/neon-scalar-cvt.ll index ef91c2e4a8..3a19bed9f6 100644 --- a/test/CodeGen/AArch64/neon-scalar-cvt.ll +++ b/test/CodeGen/AArch64/neon-scalar-cvt.ll @@ -92,46 +92,42 @@ define i32 @test_vcvts_n_s32_f32(float %a) { ; CHECK: test_vcvts_n_s32_f32 ; CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}, #1 entry: - %fcvtzs = insertelement <1 x float> undef, float %a, i32 0 - %fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.v1f32(<1 x float> %fcvtzs, i32 1) + %fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.f32(float %a, i32 1) %0 = extractelement <1 x i32> %fcvtzs1, i32 0 ret i32 %0 } -declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.v1f32(<1 x float>, i32) +declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.f32(float, i32) define i64 @test_vcvtd_n_s64_f64(double %a) { ; CHECK: test_vcvtd_n_s64_f64 ; CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}, #1 entry: - %fcvtzs = insertelement <1 x double> undef, double %a, i32 0 - %fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.v1f64(<1 x double> %fcvtzs, i32 1) + %fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.f64(double %a, i32 1) %0 = extractelement <1 x i64> %fcvtzs1, i32 0 ret i64 %0 } -declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.v1f64(<1 x double>, i32) +declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.f64(double, i32) define i32 @test_vcvts_n_u32_f32(float %a) { ; CHECK: test_vcvts_n_u32_f32 ; CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}, #32 entry: - %fcvtzu = insertelement <1 x float> undef, float %a, i32 0 - %fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.v1f32(<1 x float> %fcvtzu, i32 32) + %fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.f32(float %a, i32 32) %0 = extractelement <1 x i32> %fcvtzu1, i32 0 ret i32 %0 } -declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.v1f32(<1 x float>, i32) +declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.f32(float, i32) define i64 @test_vcvtd_n_u64_f64(double %a) { ; CHECK: test_vcvtd_n_u64_f64 ; CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}, #64 entry: - %fcvtzu = insertelement <1 x double> undef, double %a, i32 0 - %fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.v1f64(<1 x double> %fcvtzu, i32 64) + %fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.f64(double %a, i32 64) %0 = extractelement <1 x i64> %fcvtzu1, i32 0 ret i64 %0 } -declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.v1f64(<1 x double>, i32) +declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.f64(double, i32) |