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| author | Tim Northover <tnorthover@apple.com> | 2013-05-31 13:47:25 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-05-31 13:47:25 +0000 |
| commit | e93c701cac2ac62bcd390b978604da76be9967d0 (patch) | |
| tree | da4b95d57adc4fa985e00e8f78ec3a581a420234 /test/MC | |
| parent | b6606e46abad12a112a57048caec2142522bc67d (diff) | |
| download | llvm-e93c701cac2ac62bcd390b978604da76be9967d0.tar.gz llvm-e93c701cac2ac62bcd390b978604da76be9967d0.tar.bz2 llvm-e93c701cac2ac62bcd390b978604da76be9967d0.tar.xz | |
ARM: fix VEXT encoding corner case
The disassembly of VEXT instructions was too lax in the bits checked. This
fixes the case where the instruction affects Q-registers but a misaligned lane
was specified (should be UNDEFINED).
Patch by Amaury de la Vieuville
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt b/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt new file mode 100644 index 0000000000..b76485e4a5 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | grep "invalid instruction encoding" + +# invalid imm4 value (0b1xxx) +# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED; +0x8f 0xf9 0xf7 0xf2 |