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path: root/lib/Target/Hexagon/HexagonInstrInfoV4.td
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* TableGen: permit non-leaf ComplexPattern usesTim Northover2014-05-20
| | | | | | | | | | | | | | | | | | This allows the results of a ComplexPattern check to be distributed to separate named Operands, instead of the current system where all results must apply (and match perfectly) with a single Operand. For example, if "some_addrmode" is a ComplexPattern producing two results, you can write: def : Pat<(load (some_addrmode GPR64:$base, imm:$offset)), (INST GPR64:$base, imm:$offset)>; This should allow neater instruction definitions in TableGen that don't put all possible aspects of addressing into a single operand, but are still usable with relatively simple C++ CodeGen idioms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209206 91177308-0d34-0410-b5e6-96231b3b80d8
* [Hexagon] Add New TSFlags to be used in the upcoming patches.Jyotsna Verma2014-05-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208239 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typosAlp Toker2014-02-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202107 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct word hyphenationsAlp Toker2013-12-05
| | | | | | | This patch tries to avoid unrelated changes other than fixing a few hyphen-related ambiguities and contractions in nearby lines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196471 91177308-0d34-0410-b5e6-96231b3b80d8
* Prune trailing linefeeds.NAKAMURA Takumi2013-10-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193511 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add patterns to generate 'combine' instructions.Jyotsna Verma2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181805 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Set accessSize and addrMode on all load/store instructions.Jyotsna Verma2013-05-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181324 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181235 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting r180953Jyotsna Verma2013-05-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180964 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for Jump instructions.Jyotsna Verma2013-05-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180885 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.Jyotsna Verma2013-04-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Define relations for GP-relative instructions.Jyotsna Verma2013-04-23
| | | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180144 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Remove duplicate instructions to handle global/immediate valuesJyotsna Verma2013-04-23
| | | | | | | | for absolute/absolute-set addressing modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180120 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Set isPredicatedNew flag on predicate new instructions.Jyotsna Verma2013-04-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179388 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Set isPredicatedFlase flag for all the instructions with negated ↵Jyotsna Verma2013-04-12
| | | | | | predication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179387 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for gp-relative instructions.Jyotsna Verma2013-03-28
| | | | | | | | Remove noV4T gp-relative instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178246 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.Jyotsna Verma2013-03-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and ↵Jyotsna Verma2013-03-22
| | | | | | word. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add patterns for zero extended loads from i1->i64.Jyotsna Verma2013-03-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add support to lower block address.Jyotsna Verma2013-03-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting patch 176508.Jyotsna Verma2013-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add support for lowering block address.Jyotsna Verma2013-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Set appropriate TSFlags to the loads/stores with global address toJyotsna Verma2013-02-15
| | | | | | | | | | support constant extension. This patch doesn't introduce any functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175280 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for absolute addressing mode loads.Jyotsna Verma2013-02-14
| | | | | | | | This patch doesn't introduce any functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175187 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma2013-02-13
| | | | | | | | instead of redefining separate instructions for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handleJyotsna Verma2013-02-05
| | | | | | | | zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174429 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for absolute addressing mode stores.Jyotsna Verma2013-02-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174412 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add V4 compare instructions. Enable relationship mappingJyotsna Verma2013-02-05
| | | | | | | | for the existing instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174389 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add V4 combine instructions and some more Def Pats for V2.Jyotsna Verma2013-02-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174331 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats".Jyotsna Verma2013-02-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174193 91177308-0d34-0410-b5e6-96231b3b80d8
* Add appropriate TSFlags to the instructions that must be always extended.Jyotsna Verma2013-02-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174186 91177308-0d34-0410-b5e6-96231b3b80d8
* Use multiclass for post-increment store instructions.Jyotsna Verma2013-01-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173816 91177308-0d34-0410-b5e6-96231b3b80d8
* Add constant extender support for MInst type instructions.Jyotsna Verma2013-01-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173813 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove more unnecessary # operators with nothing to paste proceeding them.Craig Topper2013-01-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171702 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove # from the beginning and end of def names. The # is a paste operator ↵Craig Topper2013-01-07
| | | | | | and should only be used with something to paste on either side. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171697 91177308-0d34-0410-b5e6-96231b3b80d8
* Add constant extender support to GP-relative load/store instructions.Jyotsna Verma2012-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170672 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps.Jyotsna Verma2012-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170671 91177308-0d34-0410-b5e6-96231b3b80d8
* Use multiclass for new-value store instructions with MEMri operand.Jyotsna Verma2012-12-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169814 91177308-0d34-0410-b5e6-96231b3b80d8
* Define new-value store instructions with base+immediate addressing modeJyotsna Verma2012-12-05
| | | | | | | | using multiclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169432 91177308-0d34-0410-b5e6-96231b3b80d8
* Use multiclass to define store instructions with base+immediate offsetJyotsna Verma2012-12-05
| | | | | | | | addressing mode and immediate stored value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169408 91177308-0d34-0410-b5e6-96231b3b80d8
* Define store instructions with base+register offset addressing modeJyotsna Verma2012-12-04
| | | | | | | | using multiclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169314 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count ↵Jyotsna Verma2012-12-04
| | | | | | | | | | trailing/leading zeros) instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169287 91177308-0d34-0410-b5e6-96231b3b80d8
* Define store instructions with base+immediate offset addressing modeJyotsna Verma2012-12-03
| | | | | | | | using multiclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169168 91177308-0d34-0410-b5e6-96231b3b80d8
* Use multiclass for the store instructions with MEMri operand.Jyotsna Verma2012-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168983 91177308-0d34-0410-b5e6-96231b3b80d8
* Use multiclass for the load instructions with 'base + register offset'Jyotsna Verma2012-11-30
| | | | | | | | addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168976 91177308-0d34-0410-b5e6-96231b3b80d8
* Removing some unused instruction definitions from the Hexagon backend.Jyotsna Verma2012-11-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168388 91177308-0d34-0410-b5e6-96231b3b80d8
* Added multiclass for post-increment load instructions.Jyotsna Verma2012-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167974 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove variable_ops from call instructions in most targets.Jakob Stoklund Olesen2012-07-13
| | | | | | | | Call instructions are no longer required to be variadic, and variable_ops should only be used for instructions that encode a variable number of arguments, like the ARM stm/ldm instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160189 91177308-0d34-0410-b5e6-96231b3b80d8
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