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MC
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Author
Age
*
This reverts r155000.
Joey Gouly
2013-06-20
*
[MC] Support @ variants with directional labels
Ulrich Weigand
2013-06-20
*
[PowerPC] Optimize @ha/@l constructs
Ulrich Weigand
2013-06-20
*
[PowerPC] Support compare mnemonics with implied CR0
Ulrich Weigand
2013-06-20
*
Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU r...
Vladimir Medic
2013-06-20
*
[MC/DWARF] Generate multiple .debug_line entries for adjacent .loc directives
Ulrich Weigand
2013-06-19
*
ARM: Add optional datatype suffix to NEON mvn asm syntax.
Jim Grosbach
2013-06-18
*
Change the arm assembler to support this from the v7c spec:
Kevin Enderby
2013-06-18
*
Mips ELF: Mark object file as ABI compliant
Jack Carter
2013-06-18
*
Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.
Stefanus Du Toit
2013-06-18
*
ARM: fix literal load with positive offset encoding
Amaury de la Vieuville
2013-06-18
*
ARM: add operands pre-writeback variants when needed
Amaury de la Vieuville
2013-06-18
*
ARM: fix thumb literal loads decoding
Amaury de la Vieuville
2013-06-18
*
ARM: thumb stores cannot use PC as dest register
Amaury de la Vieuville
2013-06-18
*
AArch64: print relocation addends if present on AArch64
Tim Northover
2013-06-17
*
ARM: fix thumb coprocessor instruction with pre-writeback disassembly
Amaury de la Vieuville
2013-06-14
*
ARM: fix B decoding
Amaury de la Vieuville
2013-06-13
*
ARM: fix t2am_imm8_offset operand printing for imm=#-0
Amaury de la Vieuville
2013-06-13
*
X86: Make the cmov aliases work with intel syntax too.
Benjamin Kramer
2013-06-13
*
[MC/DWARF] Support .debug_frame / .debug_line code alignment factors
Ulrich Weigand
2013-06-12
*
[PowerPC] Use assembler source in MC tests
Ulrich Weigand
2013-06-12
*
Rework r183728, suppress assert(0) for now. Its behavior depends on assertion...
NAKAMURA Takumi
2013-06-11
*
It adds support for negative zero offsets for loads and stores.
Mihai Popa
2013-06-11
*
This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These ar...
Mihai Popa
2013-06-11
*
ARM: Enforce decoding rules for VLDn instructions
Amaury de la Vieuville
2013-06-11
*
ARM: Fix STREX/LDREX reecoding
Amaury de la Vieuville
2013-06-11
*
Tweak a couple of tests on win32 hosts with +Asserts.
NAKAMURA Takumi
2013-06-11
*
ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.
Tim Northover
2013-06-10
*
[PowerPC] Support extended sc mnemonic
Ulrich Weigand
2013-06-10
*
[PowerPC] Support branch mnemonics with implied CR0
Ulrich Weigand
2013-06-10
*
ARM: ISB cannot be passed the same options as DMB
Amaury de la Vieuville
2013-06-10
*
Fix ARM unwind opcode assembler in several cases.
Logan Chien
2013-06-09
*
ARM: fix VMOVvnf32 decoding when ambiguous with VCVT
Amaury de la Vieuville
2013-06-08
*
ARM: enforce SRS decoding constraints
Amaury de la Vieuville
2013-06-08
*
ARM: fix CPS decoding when ambiguous with QADD
Amaury de la Vieuville
2013-06-08
*
ARM: fix VCVT decoding
Amaury de la Vieuville
2013-06-08
*
Don't hide the first ELF symbol.
Rafael Espindola
2013-06-05
*
This is a simple patch that changes RRX and RRXS to accept all registers as o...
Mihai Popa
2013-06-05
*
ARM: permit upper-case BE/LE on setend instruction
Tim Northover
2013-05-31
*
ARM: add fstmx and fldmx instructions for assembly
Tim Northover
2013-05-31
*
ARM: fix VEXT encoding corner case
Tim Northover
2013-05-31
*
Change how we iterate over relocations on ELF.
Rafael Espindola
2013-05-30
*
[SystemZ] Immediate compare-and-branch support
Richard Sandiford
2013-05-29
*
Mips assembler: Improve set register alias handling
Jack Carter
2013-05-28
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[SystemZ] Register compare-and-branch support
Richard Sandiford
2013-05-28
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Add support for DWARF line number table entries for values in the instruction
Cameron Zwarich
2013-05-25
*
[SystemZ] Improve AsmParser handling of invalid instructions
Richard Sandiford
2013-05-24
*
[SystemZ] Improve AsmParser register parsing
Richard Sandiford
2013-05-24
*
VSTn instructions have a number of encoding constraints which are not impleme...
Mihai Popa
2013-05-20
*
Q registers are encoded in fields of the same length as D registers. As Q reg...
Mihai Popa
2013-05-20
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