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* Preserve MachineMemOperands in ARMLoadStoreOptimizer.Andrew Trick2011-11-11
| | | | | | | Fixes PR8113. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144409 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM allow Q registers in vldm/vstm register lists.Jim Grosbach2011-11-11
| | | | | | rdar://9672822 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
* Move X86 specific test in X86 directory.Devang Patel2011-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144395 91177308-0d34-0410-b5e6-96231b3b80d8
* Move X86 specific test in X86 directory.Devang Patel2011-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144394 91177308-0d34-0410-b5e6-96231b3b80d8
* allow non-device function calls in PTX when natively handling device-side printfDan Bailey2011-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144388 91177308-0d34-0410-b5e6-96231b3b80d8
* Add lowering for AVX2 shift instructions.Craig Topper2011-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144380 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for using immediates with select instructions.Chad Rosier2011-11-11
| | | | | | | rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144376 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.Eli Friedman2011-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144361 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of an optimization in SCCP which appears to have many issues. ↵Eli Friedman2011-11-11
| | | | | | | | | | | | Specifically, it doesn't handle many cases involving undef correctly, and it is missing other checks which lead to it trying to re-mark a value marked as a constant with a different value. It also appears to trigger very rarely. Fixes PR11357. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144352 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for using MVN to materialize negative constants.Chad Rosier2011-11-11
| | | | | | rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144348 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 parsing for push/pop w/ hi registers in the reglist.Jim Grosbach2011-11-10
| | | | | | rdar://10130228. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
* Check in getOrCreateSubprogramDIE if a declaration exists and if so outputRafael Espindola2011-11-10
| | | | | | | | it first. This is a more general fix to pr11300. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144324 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb MUL assembly parsing for 3-operand form.Jim Grosbach2011-11-10
| | | | | | | | | Get the source register that isn't tied to the destination register correct, even when the assembly source operand order is backwards. rdar://10428630 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
* When in ARM mode, LDRH/STRH require special handling of negative offsets.Chad Rosier2011-11-10
| | | | | | | For correctness, disable this for now. rdar://10418009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144316 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for LSR/LSL/ROR(immediate).Jim Grosbach2011-11-10
| | | | | | More of rdar://9704684 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for ASR(immediate).Jim Grosbach2011-11-10
| | | | | | Start of rdar://9704684 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/lsr-loop-exit-cond.ll: Try to appease linux and freebsd ↵NAKAMURA Takumi2011-11-10
| | | | | | | | bots to specify explicit -mtriple=x86_64-darwin. I guess it expects -relocation-model=pic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144290 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a bigger hammer to fix PR11314 by disabling the "forcing two-addressEvan Cheng2011-11-10
| | | | | | | | | | | | | | | | | instruction lower optimization" in the pre-RA scheduler. The optimization, rather the hack, was done before MI use-list was available. Now we should be able to implement it in a better way, perhaps in the two-address pass until a MI scheduler is available. Now that the scheduler has to backtrack to handle call sequences. Adding artificial scheduling constraints is just not safe. Furthermore, the hack is not taking all the other scheduling decisions into consideration so it's just as likely to pessimize code. So I view disabling this optimization goodness regardless of PR11314. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144267 91177308-0d34-0410-b5e6-96231b3b80d8
* For immediate encodings of icmp, zero or sign extend first. ThenChad Rosier2011-11-10
| | | | | | | determine if the value is negative and flip the sign accordingly. rdar://10422026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144258 91177308-0d34-0410-b5e6-96231b3b80d8
* Strip old implicit operands after foldMemoryOperand.Jakob Stoklund Olesen2011-11-10
| | | | | | | | | | | | The TII.foldMemoryOperand hook preserves implicit operands from the original instruction. This is not what we want when those implicit operands refer to the register being spilled. Implicit operands referring to other registers are preserved. This fixes PR11347. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144247 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing STMDB w/ optional .w suffix.Jim Grosbach2011-11-09
| | | | | | | rdar://10422955 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.Eli Friedman2011-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144241 91177308-0d34-0410-b5e6-96231b3b80d8
* DeadStoreElimination can now trim the size of a store if the end of the ↵Pete Cooper2011-11-09
| | | | | | | | | | | | store is dead. Currently checks alignment and killing stores on a power of 2 boundary as this is likely to trim the size of the earlier store without breaking large vector stores into scalar ones. Fixes <rdar://problem/10140300> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144239 91177308-0d34-0410-b5e6-96231b3b80d8
* Add check so we don't try to perform an impossible transformation. Fixes ↵Eli Friedman2011-11-09
| | | | | | issue from PR11319. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144216 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX2: Add patterns for variable shift operationsNadav Rotem2011-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144212 91177308-0d34-0410-b5e6-96231b3b80d8
* Use REs to remove dependencies on the register allocation order.Chad Rosier2011-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144209 91177308-0d34-0410-b5e6-96231b3b80d8
* Speculatively revert commit 144124 (djg) in the hope that the 32 bitDuncan Sands2011-11-09
| | | | | | | | | | | | | | | dragonegg self-host buildbot will recover (it is complaining about object files differing between different build stages). Original commit message: Add a hack to the scheduler to disable pseudo-two-address dependencies in basic blocks containing calls. This works around a problem in which these artificial dependencies can get tied up in calling seqeunce scheduling in a way that makes the graph unschedulable with the current approach of using artificial physical register dependencies for calling sequences. This fixes PR11314. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144188 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX2 support for vselect of v32i8Nadav Rotem2011-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144187 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable execution dependency fix pass for YMM registers when AVX2 is enabled. ↵Craig Topper2011-11-09
| | | | | | Add AVX2 logical operations to list of replaceable instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144179 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction selection for AVX2 integer comparisons.Craig Topper2011-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144176 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX2 instruction lowering for add, sub, and mul.Craig Topper2011-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144174 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't forget to check FlagNW when determining whether an AddRecExpr will wrapNick Lewycky2011-11-09
| | | | | | | or not. Patch by Brendon Cahoon! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144173 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for encoding immediates in icmp and fcmp. Hopefully, this willChad Rosier2011-11-09
| | | | | | | | remove a fair number of unnecessary materialized constants. rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144163 91177308-0d34-0410-b5e6-96231b3b80d8
* Collapse DomainValues across loop back-edges.Jakob Stoklund Olesen2011-11-09
| | | | | | | | | | | | | | During the initial RPO traversal of the basic blocks, remember the ones that are incomplete because of back-edges from predecessors that haven't been visited yet. After the initial RPO, revisit all those loop headers so the incoming DomainValues on the back-edges can be properly collapsed. This will properly fix execution domains on software pipelined code, like the included test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144151 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a hack to the scheduler to disable pseudo-two-address dependencies inDan Gohman2011-11-08
| | | | | | | | | | | basic blocks containing calls. This works around a problem in which these artificial dependencies can get tied up in calling seqeunce scheduling in a way that makes the graph unschedulable with the current approach of using artificial physical register dependencies for calling sequences. This fixes PR11314. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144124 91177308-0d34-0410-b5e6-96231b3b80d8
* Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ↵Evan Cheng2011-11-08
| | | | | | ldm or ldr pairs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix code to match comment. Fixes PR11340, a regression from r143209.Eli Friedman2011-11-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144121 91177308-0d34-0410-b5e6-96231b3b80d8
* LICM pass now understands invariant load metadata. Nothing generates this ↵Pete Cooper2011-11-08
| | | | | | yet so it will currently never get used in real tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144107 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding test for machine-licm operating on invariant load instructionsPete Cooper2011-11-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144104 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.Lang Hames2011-11-08
| | | | | | | | | Add support for trimming constants to GetDemandedBits. This fixes some funky constant generation that occurs when stores are expanded for targets that don't support unaligned stores natively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144102 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/vec_shuffle-39.ll: Add explicit -mtriple=x86_64-linux. ↵NAKAMURA Takumi2011-11-08
| | | | | | Passing packed value is not compatible on Win32 x64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144068 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/vec_shuffle-38.ll: Relax expression for Win32 x64.NAKAMURA Takumi2011-11-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144067 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/vec_shuffle.ll: Add explicit -mtriple=i686-linux. We may ↵NAKAMURA Takumi2011-11-08
| | | | | | see some suboptimal frame (%ebp) emission on certain hosts. Possible [PR11031] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144066 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure to mark vector extload's as expand on ARM. Fixes PR11319.Eli Friedman2011-11-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144057 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a bunch of calls to RemoveDeadNode in LegalizeDAG, so legalization ↵Eli Friedman2011-11-08
| | | | | | | | | | doesn't get confused by CSE later on. Fixes PR11318. Re-commit of r144034, with an extra fix so that RemoveDeadNode doesn't blow up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144055 91177308-0d34-0410-b5e6-96231b3b80d8
* Add x86 isel logic and patterns to match movlps from clang generated IR for ↵Evan Cheng2011-11-08
| | | | | | _mm_loadl_pi(). rdar://10134392, rdar://10050222 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144052 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert to the new EH model.Bill Wendling2011-11-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144050 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert to the new EH model.Bill Wendling2011-11-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144049 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert tests to the new EH model.Bill Wendling2011-11-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144048 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable support for returning i1, i8, and i16. Nothing special todo as it's theChad Rosier2011-11-08
| | | | | | | | | callee's responsibility to sign or zero-extend the return value. The additional test case just checks to make sure the calls are selected (i.e., -fast-isel-abort doesn't assert). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144047 91177308-0d34-0410-b5e6-96231b3b80d8
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