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* Add testcase for r199263 forgotten in commit.Eric Christopher2014-01-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199267 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: correctly determine final tBX_LR in Thumb1 functionsTim Northover2014-01-14
| | | | | | | | | | | | | The changes caused by folding an sp-adjustment into a "pop" previously disrupted the forward search for the final real instruction in a terminating block. This switches to a backward search (skipping debug instrs). This fixes PR18399. Patch by Zhaoshi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199266 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: don't try to handle [SU]MUL_LOHI nodesTim Northover2014-01-14
| | | | | | | | We should set them to expand for now since there are no patterns dealing with them. Actually, there are no instructions either so I doubt they'll ever be acceptable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199265 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-enable remote MCJIT tests on ARMv7Renato Golin2014-01-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199262 91177308-0d34-0410-b5e6-96231b3b80d8
* Do pointer cast simplifications on addrspacecastMatt Arsenault2014-01-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199254 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "[AArch64] Added vselect patterns with float and double types"Rafael Espindola2014-01-14
| | | | | | | | This reverts commit r199242. It is causing CodeGen/AArch64/neon-bsl.ll to fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199248 91177308-0d34-0410-b5e6-96231b3b80d8
* Make nocapture analysis work with addrspacecastMatt Arsenault2014-01-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199246 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a low hanging use of hasRawTextSupport.Rafael Espindola2014-01-14
| | | | | | | This also fixes the placement of the function label comment. It was being placed next to the mips16 directive instead of next to the label. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199245 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Added vselect patterns with float and double typesAna Pazos2014-01-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199242 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case micromips-load-effective-address.s renamed to ↵Zoran Jovanovic2014-01-14
| | | | | | micromips-load-effective-address.ll and moved to test/CodeGen/Mips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199221 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle dllexport for global aliasesNico Rieck2014-01-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199219 91177308-0d34-0410-b5e6-96231b3b80d8
* Decouple dllexport/dllimport from linkageNico Rieck2014-01-14
| | | | | | | | | | | | | | | | | | | Representing dllexport/dllimport as distinct linkage types prevents using these attributes on templates and inline functions. Instead of introducing further mixed linkage types to include linkonce and weak ODR, the old import/export linkage types are replaced with a new separate visibility-like specifier: define available_externally dllimport void @f() {} @Var = dllexport global i32 1, align 4 Linkage for dllexported globals and functions is now equal to their linkage without dllexport. Imported globals and functions must be either declarations with external linkage, or definitions with AvailableExternallyLinkage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199218 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: optimized scalar compare patternsElena Demikhovsky2014-01-14
| | | | | | | removed AVX512SI format, since it is similar to AVX512BI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199217 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Fix assertion failure caused by a wrong folding of vector shifts by ↵Andrea Di Biagio2014-01-14
| | | | | | | | | | | | | | | | | | | | immediate count. This fixes a regression intruced by r198113. Revision r198113 introduced an algorithm that tries to fold a vector shift by immediate count into a build_vector if the input vector is a known vector of constants. However the algorithm only worked under the assumption that the input vector type and the shift type are exactly the same. This patch disables the folding of vector shift by immediate count if the input vector type and the shift value type are not the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199213 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add constraint that RdLo != Rn != RdHi for v5 MLA insts.Tim Northover2014-01-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199212 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Decouple dllexport/dllimport from linkage"Nico Rieck2014-01-14
| | | | | | | | Revert this for now until I fix an issue in Clang with it. This reverts commit r199204. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199207 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Handle dllexport for global aliases"Nico Rieck2014-01-14
| | | | | | This reverts commit r199205. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199206 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle dllexport for global aliasesNico Rieck2014-01-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199205 91177308-0d34-0410-b5e6-96231b3b80d8
* Decouple dllexport/dllimport from linkageNico Rieck2014-01-14
| | | | | | | | | | | | | | | | | | | Representing dllexport/dllimport as distinct linkage types prevents using these attributes on templates and inline functions. Instead of introducing further mixed linkage types to include linkonce and weak ODR, the old import/export linkage types are replaced with a new separate visibility-like specifier: define available_externally dllimport void @f() {} @Var = dllexport global i32 1, align 4 Linkage for dllexported globals and functions is now equal to their linkage without dllexport. Imported globals and functions must be either declarations with external linkage, or definitions with AvailableExternallyLinkage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199204 91177308-0d34-0410-b5e6-96231b3b80d8
* Always let value types influence register classes.Jakob Stoklund Olesen2014-01-14
| | | | | | | | | | | | | | | | | | | | | When creating a virtual register for a def, the value type should be used to pick the register class. If we only use the register class constraint on the instruction, we might pick a too large register class. Some registers can store values of different sizes. For example, the x86 xmm registers can hold f32, f64, and 128-bit vectors. The three different value sizes are represented by register classes with identical register sets: FR32, FR64, and VR128. These register classes have different spill slot sizes, so it is important to use the right one. The register class constraint on an instruction doesn't necessarily care about the size of the value its defining. The value type determines that. This fixes a problem where InstrEmitter was picking 32-bit register classes for 64-bit values on SPARC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199187 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace .mips_hack_stocg with ".set micromips" and ".set nomicromips".Rafael Espindola2014-01-14
| | | | | | | This matches what gnu as does and implementing this is easier than arguing about it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199181 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix llc to not reuse spill slots in functions that invoke setjmp()Mark Seaborn2014-01-14
| | | | | | | | | | | | | | | | | | We need to ensure that StackSlotColoring.cpp does not reuse stack spill slots in functions that call "returns_twice" functions such as setjmp(), otherwise this can lead to miscompiled code, because a stack slot would be clobbered when it's still live. This was already handled correctly for functions that call setjmp() (though this wasn't covered by a test), but not for functions that invoke setjmp(). We fix this by changing callsFunctionThatReturnsTwice() to check for invoke instructions. This fixes PR18244. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199180 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up RUN command for Assembler/getInt.ll.Cameron McInally2014-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199158 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix uninitialized warning in llvm/lib/IR/DataLayout.cpp.Cameron McInally2014-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199147 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAG] Teach DAG to also reassociate vector operationsJuergen Ributzka2014-01-13
| | | | | | | | | | This commit teaches DAG to reassociate vector ops, which in turn enables constant folding of vector op chains that appear later on during custom lowering and DAG combine. Reviewed by Andrea Di Biagio git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199135 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocksWeiming Zhao2014-01-13
| | | | | | | | | | The issue is caused when Post-RA scheduler reorders a bundle instruction (IT block). However, it only flips the CPSR liveness of the bundle instruction, leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes Thumb2SizeReduction.cpp::ReduceMBB(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199127 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Fix assertion failure caused by an invalid comparison between ↵Andrea Di Biagio2014-01-13
| | | | | | | | | | | | | | APInt values. APInt only knows how to compare values with the same BitWidth and asserts in all other cases. With this fix, function PerformORCombine does not use the APInt equality operator if the APInt values returned by 'isConstantSplat' differ in BitWidth. In that case they are different and no comparison is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199119 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Flesh out stackrestore test (frame-11.ll)Richard Sandiford2014-01-13
| | | | | | | ...so that it does something vaguely sensible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199117 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add "volatile" to a dead store in variable-loc.llRichard Sandiford2014-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199116 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Improve risbg-01.ll testRichard Sandiford2014-01-13
| | | | | | | | | | | | | | | The old mask in f24 wasn't well chosen because the lshr would always be zero. CodeGen didn't detect this but InstCombine would. The new mask ensures that both shifts are needed. f26 is specifically testing for a wrap-around mask. The AND can be applied to just the shift left, either before or after the shift. Again, CodeGen kept it in the original form but InstCombine would mask after the shift instead. The exact choice of NILF isn't important for the test so I just dropped it and kept the rotate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199115 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Optimize (sext (ashr (shl ...), ...))Richard Sandiford2014-01-13
| | | | | | | | | | | ...into (ashr (shl (anyext X), ...), ...), which requires one fewer instruction. The (anyext X) can sometimes be simplified too. I didn't do this in DAGCombiner because widening shifts isn't a win on all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199114 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add test for r199108. Oops.Tim Northover2014-01-13
| | | | | | rdar://problem/15800156 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199109 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Fix retq/retl handling in 64-bit modeDavid Woodhouse2014-01-13
| | | | | | | | | | | | | | | | | | | | | | | | | This finishes the job started in r198756, and creates separate opcodes for 64-bit vs. 32-bit versions of the rest of the RET instructions too. LRETL/LRETQ are interesting... I can't see any justification for their existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no need for a REX.W prefix for LRETQ. But this is what GAS does, and my Sandybridge CPU and an Opteron 6376 concur when tested as follows: asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:"); asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:"); asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:"); asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:"); cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to match it. I don't quite understand how the Intel syntax parsing for ret instructions is working, despite r154468 allegedly fixing it. Aren't the explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at least made the 'lretq' work with (and indeed *require*) the 'q'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199106 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Embedded Rounding Control - encoding and printingElena Demikhovsky2014-01-13
| | | | | | | Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199102 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Wire up support for writing bitcode with new PM.Chandler Carruth2014-01-13
| | | | | | | | | | This moves the old pass creation functionality to its own header and updates the callers of that routine. Then it adds a new PM supporting bitcode writer to the header file, and wires that up in the opt tool. A test is added that round-trips code into bitcode and back out using the new pass manager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199078 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/ExecutionEngine/MCJIT/load-object-a.ll: Put together rm(1) and ↵NAKAMURA Takumi2014-01-13
| | | | | | mkdir(1) at the top. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199077 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Wire up support for printing assembly output from the opt command.Chandler Carruth2014-01-13
| | | | | | This lets us round-trip IR in the expected manner with the opt tool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199075 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Add missing patterns for bitcast from or to v1f64Kevin Qin2014-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199070 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Add more scenarios to use perm instructions when lowering ↵Kevin Qin2014-01-13
| | | | | | | | | | | | | | | | shuffle_vector This patch covered 2 more scenarios: 1. Two operands of shuffle_vector are the same, like %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> 2. One of operands is undef, like %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> After this patch, perm instructions will have chance to be emitted instead of lots of INS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199069 91177308-0d34-0410-b5e6-96231b3b80d8
* correct target directive handling error handlingSaleem Abdulrasool2014-01-13
| | | | | | | | | | | | | | The target specific parser should return `false' if the target AsmParser handles the directive, and `true' if the generic parser should handle the directive. Many of the target specific directive handlers would `return Error' which does not follow these semantics. This change simply changes the target specific routines to conform to the semantis of the ParseDirective correctly. Conformance to the semantics improves diagnostics emitted for the invalid directives. X86 is taken as a sample to ensure that multiple diagnostics are not presented for a single error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199068 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle bundled terminators in isBlockOnlyReachableByFallthrough.Jakob Stoklund Olesen2014-01-12
| | | | | | | | | | Targets like SPARC and MIPS have delay slots and normally bundle the delay slot instruction with the corresponding terminator. Teach isBlockOnlyReachableByFallthrough to find any MBB operands on bundled terminators so SPARC doesn't need to specialize this function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199061 91177308-0d34-0410-b5e6-96231b3b80d8
* Make test independent of schedulingNico Rieck2014-01-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199055 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/shl_undef.ll: Tweak to satisfy r199050.NAKAMURA Takumi2014-01-12
| | | | | | Use intel syntax, or "shl" might hit "pushl". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199051 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix non-deterministic SDNodeOrder-dependent codegenNico Rieck2014-01-12
| | | | | | | Reset SelectionDAGBuilder's SDNodeOrder to ensure deterministic code generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199050 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Add module and function printing passes for the new pass manager.Chandler Carruth2014-01-12
| | | | | | | | | This implements the legacy passes in terms of the new ones. It adds basic testing using explicit runs of the passes. Next up will be wiring the basic output mechanism of opt up when the new pass manager is engaged unless bitcode writing is requested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199049 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Fix a bunch of bugs I spotted by inspection when working on thisChandler Carruth2014-01-12
| | | | | | code. Copious tests added to cover these cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199039 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Add support for parsing function passes and function pass managerChandler Carruth2014-01-12
| | | | | | | | | nests to the opt commandline support. This also showcases the implicit-initial-manager support which will be most useful for testing. There are several bugs that I spotted by inspection here that I'll fix with test cases in subsequent commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199038 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: fix diagnostics of improper qualificationSaleem Abdulrasool2014-01-12
| | | | | | | | An improper qualifier would result in a superfluous error due to the parser not consuming the remainder of the statement. Simply consume the remainder of the statement to avoid the error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199035 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing floating point instructions.Venkatraman Govindaraju2014-01-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199033 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructionsSaleem Abdulrasool2014-01-12
| | | | | | | | | | | | | The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199032 91177308-0d34-0410-b5e6-96231b3b80d8
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