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* llvm-symbolizer: correctly parse filenames given in quotesAlexey Samsonov2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178859 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a basic test for llvm-symbolizer toolAlexey Samsonov2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178858 91177308-0d34-0410-b5e6-96231b3b80d8
* Add obj2yaml to test dependenciesAlexey Samsonov2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178852 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated ↵Stepan Dyatkovskiy2013-04-05
| | | | | | | | | | | | | | | | | | | instruction vldmia at incorrect position". Patch introduces memory operands tracking in ARMLoadStoreOpt::LoadStoreMultipleOpti. For each register it keeps the order of load operations as it was before optimization pass. It is kind of deep improvement of fix proposed by Hao: http://llvm.org/bugs/show_bug.cgi?id=14824#c4 But it also tracks conflicts between different register classes (e.g. D2 and S5). For more details see: Bug description: http://llvm.org/bugs/show_bug.cgi?id=14824 LLVM Commits discussion: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130311/167936.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130318/168688.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130325/169376.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130401/170238.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178851 91177308-0d34-0410-b5e6-96231b3b80d8
* The ppc bots say this is the last broken line, so lets try one more :-(Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178849 91177308-0d34-0410-b5e6-96231b3b80d8
* One more try before I just delete the macho bits until tomorrow.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178847 91177308-0d34-0410-b5e6-96231b3b80d8
* More test loosening.Rafael Espindola2013-04-05
| | | | | | Sorry for so many commits, but llvm is still building on my ppc vm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178843 91177308-0d34-0410-b5e6-96231b3b80d8
* Loosen this test too.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178841 91177308-0d34-0410-b5e6-96231b3b80d8
* Loosen this test.Rafael Espindola2013-04-05
| | | | | | | | | Looks like there is a big endian/little endian problem here. Loosen the test to try to get the bots green while llvm builds on a ppc qemu vm. The failure was in http://lab.llvm.org:8011/builders/clang-ppc64-elf-linux2/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178839 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test for obj2yaml in preparation for refactoring it.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178829 91177308-0d34-0410-b5e6-96231b3b80d8
* RegisterPressure heuristics currently require signed comparisons.Andrew Trick2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178823 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorizer: Pass OperandValueKind information to the cost modelArnold Schwaighofer2013-04-04
| | | | | | | | | | | | Pass down the fact that an operand is going to be a vector of constants. This should bring the performance of MultiSource/Benchmarks/PAQ8p/paq8p on x86 back. It had degraded to scalar performance due to my pervious shift cost change that made all shifts expensive on x86. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178809 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 cost model: Differentiate cost for vector shifts of constantsArnold Schwaighofer2013-04-04
| | | | | | | | | | | | SSE2 has efficient support for shifts by a scalar. My previous change of making shifts expensive did not take this into account marking all shifts as expensive. This would prevent vectorization from happening where it is actually beneficial. With this change we differentiate between shifts of constants and other shifts. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178808 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Improve code generation for mixed-precision reciprocal sqrtHal Finkel2013-04-04
| | | | | | | | The DAGCombine logic that recognized a/sqrt(b) and transformed it into a multiplication by the reciprocal sqrt did not handle cases where the sqrt and the division were separated by an fpext or fptrunc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178801 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable 2010-10-01-crash.ll for Hexagon as the Hexagon frontend willJyotsna Verma2013-04-04
| | | | | | | | never produce a byval parameter with size < 8 bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178792 91177308-0d34-0410-b5e6-96231b3b80d8
* Add back parsing of header charactestics.Rafael Espindola2013-04-04
| | | | | | | | It had been dropped during the switch to yaml::IO. Also add a test going from yaml2obj to llvm-readobj. It can be extended as we add more fields/formats to yaml2obj. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178786 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add bru instruction.Richard Osborne2013-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] The RRegs register class is a superset of GRRegs.Richard Osborne2013-04-04
| | | | | | | | | | At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid high-latency false CPSR dependencies even for tMOVSi.Jakob Stoklund Olesen2013-04-04
| | | | | | | | | | | | | | | | | The Thumb2SizeReduction pass avoids false CPSR dependencies, except it still aggressively creates tMOVi8 instructions because they are so common. Avoid creating false CPSR dependencies even for tMOVi8 instructions when the the CPSR flags are known to have high latency. This allows integer computation to overlap floating point computations. Also process blocks in a reverse post-order and propagate high-latency flags to successors. <rdar://problem/13468102> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178773 91177308-0d34-0410-b5e6-96231b3b80d8
* New-password-test commit.Stepan Dyatkovskiy2013-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178765 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Take export into account when computing cf addressVincent Lejeune2013-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178761 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate path to ASan/MSan symbolizer into test environment to produce ↵Alexey Samsonov2013-04-04
| | | | | | useful reports on errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178749 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SPARC v9 support for select on 64-bit compares.Jakob Stoklund Olesen2013-04-04
| | | | | | | | | | | This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178737 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 cost model: Vector shifts are expensive in most casesArnold Schwaighofer2013-04-03
| | | | | | | | | | | | | | The default logic does not correctly identify costs of casts because they are marked as custom on x86. For some cases, where the shift amount is a scalar we would be able to generate better code. Unfortunately, when this is the case the value (the splat) will get hoisted out of the loop, thereby making it invisible to ISel. radar://13130673 radar://13537826 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178703 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the "mips endian" for r_info.Rafael Espindola2013-04-03
| | | | | | | | Normally r_info is just a 32 of 64 bit number matching the endian of the rest of the file. Unfortunately, mips 64 bit little endian is special: The top 32 bits are a little endian number and the following 32 are a big endian one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178694 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Check disassembly of the st8 instruction.Richard Osborne2013-04-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178689 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Update disassembler test to improve coverage of the instructions.Richard Osborne2013-04-03
| | | | | | | Previously some instructions were unintentionally covered twice and others were not covered at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178688 91177308-0d34-0410-b5e6-96231b3b80d8
* Implements low-level object file format specific output for COFF andEric Christopher2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ELF with support for: - File headers - Section headers + data - Relocations - Symbols - Unwind data (only COFF/Win64) The output format follows a few rules: - Values are almost always output one per line (as elf-dump/coff-dump already do). - Many values are translated to something readable (like enum names), with the raw value in parentheses. - Hex numbers are output in uppercase, prefixed with "0x". - Flags are sorted alphabetically. - Lists and groups are always delimited. Example output: ---------- snip ---------- Sections [ Section { Index: 1 Name: .text (5) Type: SHT_PROGBITS (0x1) Flags [ (0x6) SHF_ALLOC (0x2) SHF_EXECINSTR (0x4) ] Address: 0x0 Offset: 0x40 Size: 33 Link: 0 Info: 0 AddressAlignment: 16 EntrySize: 0 Relocations [ 0x6 R_386_32 .rodata.str1.1 0x0 0xB R_386_PC32 puts 0x0 0x12 R_386_32 .rodata.str1.1 0x0 0x17 R_386_PC32 puts 0x0 ] SectionData ( 0000: 83EC04C7 04240000 0000E8FC FFFFFFC7 |.....$..........| 0010: 04240600 0000E8FC FFFFFF31 C083C404 |.$.........1....| 0020: C3 |.| ) } ] ---------- snip ---------- Relocations and symbols can be output standalone or together with the section header as displayed in the example. This feature set supports all tests in test/MC/COFF and test/MC/ELF (and I suspect all additional tests using elf-dump), making elf-dump and coff-dump deprecated. Patch by Nico Rieck! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178679 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement sectionContainsSymbol for ELF.Eric Christopher2013-04-03
| | | | | | Patch by Nico Rieck! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178677 91177308-0d34-0410-b5e6-96231b3b80d8
* When dumping clear the arm/thumb flag for now.Eric Christopher2013-04-03
| | | | | | Patch by Nico Rieck! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178676 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix last ALU of a clause being emitted in a separate clauseVincent Lejeune2013-04-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178675 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.Bill Schmidt2013-04-03
| | | | | | | | | For this we need to use a libcall. Previously LLVM didn't implement libcall support for frem, so I've added it in the usual straightforward manner. A test case from the bug report is included. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178639 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: implement ETMv4 trace system registers.Tim Northover2013-04-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily relax the WIN32 checks in the SRet test to fix the Atom D2700 botTimur Iskhodzhanov2013-04-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178635 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SRet for thiscall in i686-pc-win32Timur Iskhodzhanov2013-04-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178634 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 64-bit compare + branch for SPARC v9.Jakob Stoklund Olesen2013-04-03
| | | | | | | | | | The same compare instruction is used for 32-bit and 64-bit compares. It sets two different sets of flags: icc and xcc. This patch adds a conditional branch instruction using the xcc flags for 64-bit compares. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178621 91177308-0d34-0410-b5e6-96231b3b80d8
* Use PPC reciprocal estimates with Newton iteration in fast-math modeHal Finkel2013-04-03
| | | | | | | | | | | | | | | | | | | When unsafe FP math operations are enabled, we can use the fre[s] and frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together with some Newton iteration, in order to quickly generate floating-point division and sqrt results. All of these instructions are separately optional, and so each has its own feature flag (except for the Altivec instructions, which are covered under the existing Altivec flag). Doing this is not only faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these computations to be pipelined with other computations in order to hide their overall latency. I've also added a couple of missing fnmsub patterns which turned out to be missing (but are necessary for good code generation of the Newton iterations). Altivec needs a similar fix, but that will probably be more complicated because fneg is expanded for Altivec's v4f32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178617 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the fde encoding used by mips to match gas.Rafael Espindola2013-04-03
| | | | | | | | | | | | | This finally fixes the encoding. The patch also * Removes eh-frame.ll. It was an unnecessary .ll to .o test that was checking the wrong value. * Merge fde-reloc.s and eh-frame.s into a single test, since the only difference was the run lines. * Don't blindly test the content of the entire .eh_frame section. It makes it hard to anyone actually fixing a bug and hitting a difference in a binary blob. Instead, use a CHECK for each field and document what is being checked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178615 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an optimization where we were changing an objc_autorelease into an ↵Michael Gottesman2013-04-03
| | | | | | | | | | | | | | | | | | | | | objc_autoreleaseReturnValue. The semantics of ARC implies that a pointer passed into an objc_autorelease must live until some point (potentially down the stack) where an autorelease pool is popped. On the other hand, an objc_autoreleaseReturnValue just signifies that the object must live until the end of the given function at least. Thus objc_autorelease is stronger than objc_autoreleaseReturnValue in terms of the semantics of ARC* implying that performing the given strength reduction without any knowledge of how this relates to the autorelease pool pop that is further up the stack violates the semantics of ARC. *Even though objc_autoreleaseReturnValue if you know that no RV optimization will occur is more computationally expensive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178612 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Small update to the implementation of eh.return for Mips.Akira Hatanaka2013-04-02
| | | | | | | | | | | This patch initializes t9 to the handler address, but only if the relocation model is pic. This handles the case where handler to which eh.return jumps points to the start of the function. Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178588 91177308-0d34-0410-b5e6-96231b3b80d8
* Support and test template arguments for unions.Eric Christopher2013-04-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178586 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86: Unmark them out of XFAIL:cygming, in atomic{32|64}.ll ↵NAKAMURA Takumi2013-04-02
| | | | | | | | and handle-move.ll, corresponding to r178549. This reverts r176808, r176798, and r177914. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178583 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR15630: Replace faulty stdcx. with stwcx.Bill Schmidt2013-04-02
| | | | | | | | | | | When doing a partword atomic operation, a lwarx was being paired with a stdcx. instead of a stwcx. when compiling for a 64-bit target. The target has nothing to do with it in this case; we always need a stwcx. Thanks to Kai Nacke for reporting the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178559 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't attempt MTM heuristics without a scheduling model present.Jakob Stoklund Olesen2013-04-02
| | | | | | This should fix the PPC buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178558 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Use the correct API to disable FastLowerArguments for Win64.Chad Rosier2013-04-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178549 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: Merge store/loads when we have extload/truncstoresArnold Schwaighofer2013-04-02
| | | | | | | | | | | | | | | | This is helps on architectures where i8,i16 are not legal but we have byte, and short loads/stores. Allowing us to merge copies like the one below on ARM. copy(char *a, char *b, int n) { do { int t0 = a[0]; int t1 = a[1]; b[0] = t0; b[1] = t1; radar://13536387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178546 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify test cases for Atom preferring call register indirect overPreston Gurd2013-04-02
| | | | | | | | call memory indirect (32 and 64 bit). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178541 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a worklist to avoid a sneaky iterator invalidation.Bill Wendling2013-04-02
| | | | | | | | | | | | | | The iterator could be invalidated when it's recursively deleting a whole bunch of constant expressions in a constant initializer. Note: This was only reproducible if `opt' was run on a `.bc' file. If `opt' was run on a `.ll' file, it wouldn't crash. This is why the test first pushes the `.ll' file through `llvm-as' before feeding it to `opt'. PR15440 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178531 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 64-bit load and store instructions.Jakob Stoklund Olesen2013-04-02
| | | | | | There is only a few new instructions, the rest is handled with patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178528 91177308-0d34-0410-b5e6-96231b3b80d8
* Basic 64-bit ALU operations.Jakob Stoklund Olesen2013-04-02
| | | | | | | SPARC v9 extends all ALU instructions to 64 bits, so we simply need to add patterns to use them for both i32 and i64 values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178527 91177308-0d34-0410-b5e6-96231b3b80d8
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