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* Teach llvm-size to know about Mach-O universal files (aka fat files) andKevin Enderby2014-06-18
| | | | | | | | | | | fat files containing archives. Also fix a bug in MachOUniversalBinary::ObjectForArch::ObjectForArch() where it needed a >= when comparing the Index with the number of objects in a fat file. As the index starts at 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211230 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Handle fnearbyintMatt Arsenault2014-06-18
| | | | | | | | The difference from rint isn't really relevant here, so treat them as equivalent. OpenCL doesn't have nearbyint, so this is sort of pointless other than for completeness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211229 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: add gather4 and getlod intrinsics (v3)Marek Olsak2014-06-18
| | | | | | | | | | This contains all the previous patches + getlod support on top of it. It doesn't use SDNodes anymore, so it's quite small. It also adds v16i8 to SReg_128, which is used for the sampler descriptor. Reviewed-by: Tom Stellard git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211228 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: do not add comment string to the AsmToken in AsmLexer::LexLineCommentSaleem Abdulrasool2014-06-18
| | | | | | | | Fixes macros with varargs if the macro instantiation has a trailing comment. Patch by Janne Grunau! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211219 91177308-0d34-0410-b5e6-96231b3b80d8
* MCAsmParser: full support for gas' '.if{cond} expression' directivesSaleem Abdulrasool2014-06-18
| | | | | | Patch by Janne Grunau! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211218 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand vector fceilJan Vesely2014-06-18
| | | | | | | | | | Move fp64 fceil tests to fceil64.ll v2: rebase Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211194 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Simplify and improve loading into TOC registerUlrich Weigand2014-06-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During an indirect function call sequence on the 64-bit SVR4 ABI, generate code must load and then restore the TOC register. This does not use a regular LOAD instruction since the TOC register r2 is marked as reserved. Instead, the are two special instruction patterns: let RST = 2, DS = 2 in def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg), "ld 2, 8($reg)", IIC_LdStLD, [(PPCload_toc i64:$reg)]>, isPPC64; let RST = 2, DS = 10, RA = 1 in def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), "ld 2, 40(1)", IIC_LdStLD, [(PPCtoc_restore)]>, isPPC64; Note that these not only restrict the destination of the load to r2, but they also restrict the *source* of the load to particular address combinations. The latter is a problem when we want to support the ELFv2 ABI, since there the TOC save slot is no longer at 40(1). This patch replaces those two instructions with a single instruction pattern that only hard-codes r2 as destination, but supports generic addresses as source. This will allow supporting the ELFv2 ABI, and also helps generate more efficient code for calls to absolute addresses (allowing simplification of the ppc64-calls.ll test case). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211193 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add back test case for absolute calls (removed in r211174)Ulrich Weigand2014-06-18
| | | | | | | | | | As requested by Hal Finkel, this adds back a test for calls to a known-constant function pointer value, and verifies that the 64-bit SVR4 indirect function call sequence is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211190 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a triple so that right syntax is choosen on mac osx systemsArnold Schwaighofer2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211188 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211187 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Prettier operand printing for 64-bit ops.Matt Arsenault2014-06-18
| | | | | | Copy what is done for 32-bit already so the order is about the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211186 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] SYNC $stype instruction was added in Mips32Matheus Almeida2014-06-18
| | | | | | | but SYNC with an implied operand ($stype = 0) is valid since Mips2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211185 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Implement f64 ftrunc, ffloor and fceil.Matt Arsenault2014-06-18
| | | | | | CI has instructions for these, so this fixes them for older hardware. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211183 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Custom lower f64 frint for pre-CIMatt Arsenault2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211182 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] AVX512: Add non-temporal storesAdam Nemet2014-06-18
| | | | | | | | | | | Note that I followed the AVX2 convention here and didn't add LLVM intrinsics for stores. These can be generated with the nontemporal hint on LLVM IR stores (see new test). The GCC builtins are lowered directly into nontemporal stores. <rdar://problem/17082571> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211176 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] AVX512: Specify compressed displacement for vmovntdqaAdam Nemet2014-06-18
| | | | | | | Use the max 64-bit element size with EVEX_CD8. This should work since element size is ignored for a full-vector access (FVM). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211175 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Do not use BLA with the 64-bit SVR4 ABIUlrich Weigand2014-06-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The PowerPC back-end uses BLA to implement calls to functions at known-constant addresses, which is apparently used for certain system routines on Darwin. However, with the 64-bit SVR4 ABI, this is actually incorrect. An immediate function pointer value on this platform is not directly usable as a target address for BLA: - in the ELFv1 ABI, the function pointer value refers to the *function descriptor*, not the code address - in the ELFv2 ABI, the function pointer value refers to the global entry point, but BL(A) would only be correct when calling the *local* entry point This bug didn't show up since using immediate function pointer values is not usually done in the 64-bit SVR4 ABI in the first place. However, I ran into this issue with a certain use case of LLVM as JIT, where immediate function pointer values were uses to implement callbacks from JITted code to helpers in statically compiled code. Fixed by simply not using BLA with the 64-bit SVR4 ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211174 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not XFAIL test/tools/llvm-cov tests on powerpc64leUlrich Weigand2014-06-18
| | | | | | | | | | | | | All tests in test/tools/llvm-cov fail on big-endian targets and are supposed to be XFAILed there. However, including "powerpc64" in the XFAIL line is now incorrect, since that matches both powerpc64- and powerpc64le- targets, and the tests pass on the latter. Update the XFAIL lines to use powerpc64- instead (like mips64-). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211172 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix expansion of memory operation if destination register is not a GPR.Matheus Almeida2014-06-18
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The assembler tries to reuse the destination register for memory operations whenever it can but it's not possible to do so if the destination register is not a GPR. Example: ldc1 $f0, sym should expand to: lui $at, %hi(sym) ldc1 $f0, %lo(sym)($at) It's entirely wrong to expand to: lui $f0, %hi(sym) ldc1 $f0, %lo(sym)($f0) Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4173 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211169 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Report correct location when "erroring" about the use of $at when ↵Matheus Almeida2014-06-18
| | | | | | | | | | | | | | it's not available. Summary: This removes the FIXMEs from test/MC/Mips/mips-noat.s. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4172 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211168 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Add BLTC and BLTUC instructionsZoran Jovanovic2014-06-18
| | | | | | | Differential Revision: http://reviews.llvm.org/D3923 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211167 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Access $at only if necessary.Matheus Almeida2014-06-18
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch doesn't really change the logic behind expandMemInst but it allows us to assemble .S files that use .set noat with some macros. For example: .set noat lw $k0, offset($k1) Can expand to: lui $k0, %hi(offset) addu $k0, $k0, $k1 lw $k0, %lo(offset)($k0) with no need to access $at. Reviewers: dsanders, vmedic Reviewed By: dsanders, vmedic Differential Revision: http://reviews.llvm.org/D4159 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211165 91177308-0d34-0410-b5e6-96231b3b80d8
* Add pattern for unsigned v4i32->v4f64 convert on AVX512.Cameron McInally2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211164 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Update MipsAsmParser so that it's possible to handle immediates that ↵Matheus Almeida2014-06-18
| | | | | | | | | | | | start with the binary operator NOT (~). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4158 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211163 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Implement alias for 'and' and 'or' instructions for all ISAs.Matheus Almeida2014-06-18
| | | | | | | | | | | | | | | Summary: Examples: and $2, 4 <=> andi $2, $2, 4 or $2, 4 <=> ori $2, $2, 4 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4155 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211161 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Remove the last usage of parseRegister from MipsAsmParser.Matheus Almeida2014-06-18
| | | | | | | | | | | | | | Summary: Added negative test case so that we can be sure we handle erroneous situations while parsing the .cpsetup directive. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3681 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211160 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Implement 64bit SRAJan Vesely2014-06-18
| | | | | | | | v2: Use capitalized variable name Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211159 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Implement 64bit SRLJan Vesely2014-06-18
| | | | | | | | v2: use C++ style comment Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211158 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Implement 64bit SHLJan Vesely2014-06-18
| | | | | | | | v2: Use c++ style comment Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211157 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Handle X86 *.psad.* and *.pmadd.* intrinsics.Evgeniy Stepanov2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211156 91177308-0d34-0410-b5e6-96231b3b80d8
* DAG: move sret demotion into most basic LowerCallTo implementation.Tim Northover2014-06-18
| | | | | | | | | | | | | | | | It looks like there are two versions of LowerCallTo here: the SelectionDAGBuilder one is designed to operate on LLVM IR, and the TargetLowering one in the case where everything is at DAG level. Previously, only the SelectionDAGBuilder variant could handle demoting an impossible return to sret semantics (before delegating to the TargetLowering version), but this functionality is also useful for certain libcalls (e.g. 128-bit operations on 32-bit x86). So this commit moves the sret handling down a level. rdar://problem/17242889 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211155 91177308-0d34-0410-b5e6-96231b3b80d8
* [llvm-readobj][ELF] New `-mips-plt-got` command line option to outputSimon Atanasyan2014-06-18
| | | | | | | | MIPS GOT section. Patch reviewed by Rafael Espindola. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211150 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Fix a pattern match failure caused by creating improper CONCAT_VECTOR.Kevin Qin2014-06-18
| | | | | | | | | ReconstructShuffle() may wrongly creat a CONCAT_VECTOR trying to concat 2 of v2i32 into v4i16. This commit is to fix this issue and try to generate UZP1 instead of lots of MOV and INS. Patch is initalized by Kevin Qin, and refactored by Tim Northover. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211144 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow X86FastIsel to cope with 64 bit absolute relocationsLouis Gerbarg2014-06-17
| | | | | | | | | | | | This patch is a follow up to r211040 & r211052. Rather than bailing out of fast isel this patch will generate an alternate instruction (movabsq) instead of the leaq. While this will always have enough room to handle the 64 bit displacment it is generally over kill for internal symbols (most displacements will be within 32 bits) but since we have no way of communicating the code model to the the assmebler in order to avoid flagging an absolute leal/leaq as illegal when using a symbolic displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211130 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Optimize predicates and fold CMP instructions.Juergen Ributzka2014-06-17
| | | | | | | | | This optimizes predicates for certain compares, such as fcmp oeq %x, %x to fcmp ord %x, %x. The latter one is more efficient to generate. The same optimization is applied to conditional branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211126 91177308-0d34-0410-b5e6-96231b3b80d8
* Add "-format darwin" to llvm-size to be like darwin's size(1) -m output, andKevin Enderby2014-06-17
| | | | | | | | | | | | | | | | and the -l option for the long format. Also when the object is a Mach-O file and the format is berkeley produce output like darwin’s default size(1) summary berkeley derived output. Like System V format, there are also some small changes in how and where the file names and archive member names are printed for darwin and Mach-O. Like the changes to llvm-nm these are the first steps in seeing if it is possible to make llvm-size produce the same output as darwin's size(1). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211117 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Match cttz_zero_undefMatt Arsenault2014-06-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211116 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211115 91177308-0d34-0410-b5e6-96231b3b80d8
* mark the old jit tests as unsupported for powerpc64 (for cmake)Will Schmidt2014-06-17
| | | | | | | | | | mark the old JIT tests as unsupported for powerpc64 - CMake style. This follows the style used for hexagon/arm64/aarch64. The equivalent tests still run under the supported MCJIT/* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211111 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211110 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Expand i64 = FP_TO_SINT i32Tom Stellard2014-06-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211108 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Fix previous refactoring commit (r211077)Juergen Ributzka2014-06-17
| | | | | | | Overlooked that fcmp_une uses an "or" instead of an "and" for combining the flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211104 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed jump threading going to infinite loop.Dinesh Dwivedi2014-06-17
| | | | | | | | | | | This patch add code to remove unreachable blocks from function as they may cause jump threading to stuck in infinite loop. Differential Revision: http://reviews.llvm.org/D3991 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211103 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: estimate inline asm length during branch relaxationTim Northover2014-06-17
| | | | | | | | | | | | | To make sure branches are in range, we need to do a better job of estimating the length of an inline assembly block than "it's probably 1 instruction, who'd write asm with more than that?". Fortunately there's already a (highly suspect, see how many ways you can think of to break it!) callback for this purpose, which is used by the other targets. rdar://problem/17277590 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211095 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Fix handling of multiplication by a constant with a number of ↵Evgeniy Stepanov2014-06-17
| | | | | | | | | | | | | | | | | | | | trailing zeroes. Multiplication by an integer with a number of trailing zero bits leaves the same number of lower bits of the result initialized to zero. This change makes MSan take this into account in the case of multiplication by a compile-time constant. We don't handle the general, non-constant, case because (a) it's not going to be cheap (computation-wise); (b) multiplication by a partially uninitialized value in user code is a bad idea anyway. Constant case must be handled because it appears from LLVM optimization of a completely valid user code, as the test case in compiler-rt demonstrates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211092 91177308-0d34-0410-b5e6-96231b3b80d8
* [InstCombine] mark ADD with nuw if no unsigned overflowJingyue Wu2014-06-17
| | | | | | | | | | | | | | | | | | | | | | Summary: As a starting step, we only use one simple heuristic: if the sign bits of both a and b are zero, we can prove "add a, b" do not unsigned overflow, and thus convert it to "add nuw a, b". Updated all affected tests and added two new tests (@zero_sign_bit and @zero_sign_bit2) in AddOverflow.ll Test Plan: make check-all Reviewers: eliben, rafael, meheff, chandlerc Reviewed By: chandlerc Subscribers: chandlerc, llvm-commits Differential Revision: http://reviews.llvm.org/D4144 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211084 91177308-0d34-0410-b5e6-96231b3b80d8
* SROA: Only split loads on byte boundariesDuncan P. N. Exon Smith2014-06-17
| | | | | | | | | | | | | r199771 accidently broke the logic that makes sure that SROA only splits load on byte boundaries. If such a split happens, some bits get lost when reassembling loads of wider types, causing data corruption. Move the width check up to reject such splits early, avoiding the corruption. Fixes PR19250. Patch by: Björn Steinbrink <bsteinbr@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211082 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Refactor the code to get the X86 condition from a helper ↵Juergen Ributzka2014-06-16
| | | | | | | | | function. NFC. Make use of helper functions to simplify the branch and compare instruction selection in FastISel. Also add test cases for compare and conditonal branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211077 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach LoopUnrollPass to respect loop unrolling hints in metadata.Eli Bendersky2014-06-16
| | | | | | | | | | | | | | | [This is resubmitting r210721, which was reverted due to suspected breakage which turned out to be unrelated]. Some extra review comments were addressed. See D4090 and D4147 for more details. The Clang change that produces this metadata was committed in r210667 Patch by Mark Heffernan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211076 91177308-0d34-0410-b5e6-96231b3b80d8
* Add load/store functionalityReed Kotler2014-06-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patches allows non conversions like i1=i2; where both are global ints. In addition, arithmetic and other things start to work since fast-isel will use existing patterns for non fast-isel from tablegen files where applicable. In addition i8, i16 will work in this limited context for assignment without the need for sign extension (zero or signed). It does not matter how i8 or i16 are loaded (zero or sign extended) since only the 8 or 16 relevant bits are used and clang will ask for sign extension before using them in arithmetic. This is all made more complete in forthcoming patches. for example: int i, j=1, k=3; void foo() { i = j + k; } Keep in mind that this pass is not enabled right now and is an experimental pass It can only be enabled with a hidden option to llvm of -mips-fast-isel. Test Plan: Run test-suite, loadstore2.ll and I will run some executable tests. Reviewers: dsanders Subscribers: mcrosier Differential Revision: http://reviews.llvm.org/D3856 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211061 91177308-0d34-0410-b5e6-96231b3b80d8
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