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* R600: Try to convert BFE back to standard bit ops when possible.Matt Arsenault2014-05-22
| | | | | | | This allows existing DAG combines to work on them, and then we can re-match to BFE if necessary during instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209462 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add dag combine for BFEMatt Arsenault2014-05-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209461 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Implement ComputeNumSignBitsForTargetNode for BFEMatt Arsenault2014-05-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209460 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand mul24 for GPUs without itMatt Arsenault2014-05-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209458 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand mad24 for GPUs without itMatt Arsenault2014-05-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209457 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add intrinsics for mad24Matt Arsenault2014-05-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209456 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Improve the lowering of BITCAST from MVT::f64 to MVT::v4i16/MVT::v8i8.Andrea Di Biagio2014-05-22
| | | | | | | | | | | | | | | This patch teaches the x86 backend how to efficiently lower ISD::BITCAST dag nodes from MVT::f64 to MVT::v4i16 (and vice versa), and from MVT::f64 to MVT::v8i8 (and vice versa). This patch extends the logic from revision 208107 to also handle MVT::v4i16 and MVT::v8i8. Also, this patch correctly propagates Undef values when performing the widening of a vector (example: when widening from v2i32 to v4i32, the upper 64bits of the resulting vector are 'undef'). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209451 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for missed and analysis optimization remarks.Diego Novillo2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds two new diagnostics: -pass-remarks-missed and -pass-remarks-analysis. They take the same values as -pass-remarks but are intended to be triggered in different contexts. -pass-remarks-missed is used by LLVMContext::emitOptimizationRemarkMissed, which passes call when they tried to apply a transformation but couldn't. -pass-remarks-analysis is used by LLVMContext::emitOptimizationRemarkAnalysis, which passes call when they want to inform the user about analysis results. The patch also: 1- Adds support in the inliner for the two new remarks and a test case. 2- Moves emitOptimizationRemark* functions to the llvm namespace. 3- Adds an LLVMContext argument instead of making them member functions of LLVMContext. Reviewers: qcolombet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3682 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209442 91177308-0d34-0410-b5e6-96231b3b80d8
* Segmented stacks: omit __morestack call when there's no frame.Tim Northover2014-05-22
| | | | | | Patch by Florian Zeitz git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209436 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: separate load/store operands to simplify assemblerTim Northover2014-05-22
| | | | | | | | | | | | | | | | | | | This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209425 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Make unalignedload.ll test stricter and easier to modify for ↵Daniel Sanders2014-05-22
| | | | | | | | | | | | | | | | | | | | | | MIPS32r6/MIPS64r6 Summary: * Split into two functions, one to test each struct. * R0 and R2 must be defined by an lw with a %got reference to the correct symbol. * Test for $4 (first argument) where appropriate instead of accepting any register. * Test that the two lbu's are correctly combined into $4 Depends on D3844 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3845 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209424 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Change lwl and lwr in inlineasm_constraint.ll to lwDaniel Sanders2014-05-22
| | | | | | | | | | | | | | | | | Summary: lwl and lwr are not available in MIPS32r6/MIPS64r6. The purpose of the test is to check that the '$1' expands to '0($x)' rather than to test something related to the lwl or lwr instructions so we can simply switch to lw. Depends on D3842 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209423 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use addiu in inline assembly tests since addi is not available in all ↵Daniel Sanders2014-05-22
| | | | | | | | | | | | | | | | | | | | | ISA's Summary: This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when -integrated-as is enabled by default and we correctly detect the host CPU. No functional change since these tests are testing the behaviour of the constraint used for the third operand rather than the mnemonic. Depends on D3842 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3843 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209421 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-05-22
| | | | | | | | | | | | Summary: Depends on D3787. Tablegen will raise an assertion without it. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3842 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209419 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Test that paired single instructions are invalidDaniel Sanders2014-05-22
| | | | | | | | | | | | | | Summary: These emit the 'unknown instruction' instead of the correct error because they have not been implemented in LLVM for any MIPS ISA. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3841 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209418 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Add b[on]vcDaniel Sanders2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209415 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: enable more AArch64 tests.Tim Northover2014-05-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209408 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: introduce llvm.arm.undefined intrinsicSaleem Abdulrasool2014-05-22
| | | | | | | | | | | | This intrinsic permits the emission of platform specific undefined sequences. ARM has reserved the 0xde opcode which takes a single integer parameter (ignored by the CPU). This permits the operating system to implement custom behaviour on this trap. The llvm.arm.undefined intrinsic is meant to provide a means for generating the target specific behaviour from the frontend. This is particularly useful for Windows on ARM which has made use of a series of these special opcodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209390 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Match fp_to_uint / uint_to_fp for f64Matt Arsenault2014-05-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209388 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: formalise some assertions into proper errorsSaleem Abdulrasool2014-05-22
| | | | | | | | | Now that clang can be used as an assembler via the IAS, invalid assembler inputs would cause the assertions to trigger. Although we cannot recover from the errors here, nor provide caret diagnostics, attempt to handle them slightly more gracefully by reporting a fatal error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209387 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in SCEV's backedge taken count computation from my prior fix in Jan.Andrew Trick2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This has to do with the trip count computation for loops with multiple exits, which is quite subtle. Most passes just ask for a single trip count number, so we must be conservative assuming any exit could be taken. Normally, we rely on the "exact" trip count, which was correctly given as "unknown". However, SCEV also gives a "max" back-edge taken count. The loops max BE taken count is conservatively a maximum over the max of each exit's non-exiting iterations count. Note that some exit tests can be skipped so the max loop back-edge taken count can actually exceed the max non-exiting iterations for some exits. However, when we know the loop *latch* cannot be skipped, we can directly use its max taken count disregarding other exits. I previously took the minimum here without checking whether the other exit could be skipped. The correct, and simpler thing to do here is just to directly use the loop latch's max non-exiting iterations as the loops max back-edge count. In the problematic test case, the first loop exit had a max of zero non-exiting iterations, but could be skipped. The loop latch was known not to be skipped but had max of one non-exiting iteration. We incorrectly claimed the loop back-edge could be taken zero times, when it is actually taken one time. Fixes Loop %for.body.i: <multiple exits> Unpredictable backedge-taken count. Loop %for.body.i: max backedge-taken count is 1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209358 91177308-0d34-0410-b5e6-96231b3b80d8
* Similar to bitcast, treat addrspacecast as a foldable operand.Eli Bendersky2014-05-22
| | | | | | | | | Added a test sink-addrspacecast.ll to verify this change. Patch by Jingyue Wu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209343 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "DebugInfo: Don't put fission type units in comdat sections."David Blaikie2014-05-21
| | | | | | | | | This reverts commit r208930, r208933, and r208975. It seems not all fission consumers are ready to handle this behavior. Reverting until tools are brought up to spec. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209338 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: correct IMAGE_REL_ARM_MOV32T relocation emissionSaleem Abdulrasool2014-05-21
| | | | | | | | | | | | This corrects the emission of IMAGE_REL_ARM_MOV32T relocations. Previously, we were avoiding the high portion of the relocation too early. If there was a section-relative relocation with an offset greater than 16-bits (65535), you would end up truncating the high order bits of the offset. Allow the current relocation representation to flow through out the MC layer to the object writer. Use the new ability to restrict recorded relocations to avoid emitting the relocation into the final object. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209337 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Use the SPMap to find the parent CU of inlined functions as they ↵David Blaikie2014-05-21
| | | | | | | | | | | | | | | | may not be in the current CU Committed in r209178 then reverted in r209251 due to LTO breakage, here's a proper fix for the case of the missing subprogram DIE. The DIEs were there, just in other compile units. Using the SPMap we can find the right compile unit to search for and produce cross-unit references to describe this kind of inlining. One existing test case needed to be updated because it had a function that wasn't in the CU's subprogram list, so it didn't appear in the SPMap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209335 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Partially fix constant initializers for structs and vectors.Matt Arsenault2014-05-21
| | | | | | | This should extend the current workaround to work with structs that only contain legal, scalar types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209331 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add failing testcases for constant initializers.Matt Arsenault2014-05-21
| | | | | | | | Constant initializers involving illegal types hit an assertion. Patch by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209330 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Ensure concrete out of line variables from inlined functions ↵David Blaikie2014-05-21
| | | | | | reference their abstract origins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209327 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Fix a bug in the lowering of BLENDI introduced in r209043.Quentin Colombet2014-05-21
| | | | | | | | | | | | | | | | | | | | ISD::VSELECT mask uses 1 to identify the first argument and 0 to identify the second argument. On the other hand, BLENDI uses 0 to identify the first argument and 1 to identify the second argument. Fix the generation of the blend mask to account for this difference. The bug did not show up with r209043, because we were not checking for the actual arguments of the blend instruction! This commit also fixes the test cases. Note: The same mask works for the BLENDr variant because the arguments are swapped during instruction selection (see the BLENDXXrr patterns). <rdar://problem/16975435> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209324 91177308-0d34-0410-b5e6-96231b3b80d8
* Move MCOptions that aren't shared between programs into their specificEric Christopher2014-05-21
| | | | | | program and have them initialize the MCOptions struct explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209321 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Simplify subprogram declaration creation/references and ↵David Blaikie2014-05-21
| | | | | | | | accidentally refix PR11300. Also simplifies the linkage name handling a little too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209311 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: loosen an overzealous assertionSaleem Abdulrasool2014-05-21
| | | | | | | | Permit active macro expansions when terminating the assembler if there were errors during the expansion. This would only trigger on invalid input when built with assertions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209309 91177308-0d34-0410-b5e6-96231b3b80d8
* Test comment commit.Dave Estes2014-05-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209306 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Add bc[12](eq|ne)zDaniel Sanders2014-05-21
| | | | | | | | | | | | Summary: Depends on D3691 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3760 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209292 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: mark COFF .drectve section as REMOVESaleem Abdulrasool2014-05-21
| | | | | | | | | The .drectve section should be marked as IMAGE_SCN_LNK_REMOVE. This matches what the MSVC toolchain does and accurately reflects that this section should not be emitted into the final binary. This section is merely information for the linker, comprising of additional linker directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209273 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: correct bundle generation for MOV32T relocationsSaleem Abdulrasool2014-05-21
| | | | | | | | | | | | | | | | | | | | | | | Although the previous code would construct a bundle and add the correct elements to it, it would not finalise the bundle. This resulted in the InternalRead markers not being added to the MachineOperands nor, more importantly, the externally visible defs to the bundle itself. So, although the bundle was not exposing the def, the generated code would be correct because there was no optimisations being performed. When optimisations were enabled, the post register allocator would kick in, and the hazard recognizer would reorder operations around the load which would define the value being operated upon. Rather than manually constructing the bundle, simply construct and finalise the bundle via the finaliseBundle call after both MIs have been emitted. This improves the code generation with optimisations where IMAGE_REL_ARM_MOV32T relocations are emitted. The changes to the other tests are the result of the bundle generation preventing the scheduler from hoisting the moves across the loads. The net effect of the generated code is equivalent, but, is much more identical to what is actually being lowered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209267 91177308-0d34-0410-b5e6-96231b3b80d8
* This command line option is only used in one place. Move it there andEric Christopher2014-05-21
| | | | | | rename it to something more descriptive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209263 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a comment here.Eric Christopher2014-05-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209262 91177308-0d34-0410-b5e6-96231b3b80d8
* Move this test to the backend from the frontend.Eric Christopher2014-05-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209259 91177308-0d34-0410-b5e6-96231b3b80d8
* Update MachOObjectFile::getSymbolAddress so it returns UnknownAddressOrSizeKevin Enderby2014-05-20
| | | | | | | | | | | | | for undefined symbols, so it matches what COFFObjectFile::getSymbolAddress does. This allows llvm-nm to print spaces instead of 0’s for the value of undefined symbols in Mach-O files. To make this change other uses of MachOObjectFile::getSymbolAddress are updated to handle when the Value is returned as UnknownAddressOrSize. Which is needed to keep two of the ExecutionEngine tests working for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209253 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test added in r209242: llc shouldn't create files in source treeAlexey Samsonov2014-05-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209252 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] PR19792: Fix cycle in DAG after performPostLD1CombineAdam Nemet2014-05-20
| | | | | | | | | | | | | | | | | | | Povray and dealII currently assert with "Overran sorted position" in AssignTopologicalOrder. The problem is that performPostLD1Combine can introduce cycles. Consider: (insert_vector_elt (INSERT_SUBREG undef, (load (add %vreg0, Constant<8>), undef), <= A TargetConstant<2>), (load %vreg0, undef), <= B Constant<1>) This is turned into a LD1LANEpost node. However the address in A is not a valid user of the post-incremented address of B in LD1LANEpost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209242 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the function and data section flags into the options struct andEric Christopher2014-05-20
| | | | | | | | | | make the functions to set them non-static. Move and rename the llvm specific backend options to avoid conflicting with the clang option. Paired with a backend commit to update. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209238 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r209235 as it broke two tests:Kevin Enderby2014-05-20
| | | | | | | | | Failing Tests (2): LLVM :: ExecutionEngine/MCJIT/stubs-sm-pic.ll LLVM :: ExecutionEngine/MCJIT/stubs.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209236 91177308-0d34-0410-b5e6-96231b3b80d8
* Update MachOObjectFile::getSymbolAddress so it returns UnknownAddressOrSizeKevin Enderby2014-05-20
| | | | | | | | for undefined symbols. Allowing llvm-nm to print spaces instead of 0’s for the value of undefined symbols in Mach-O files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209235 91177308-0d34-0410-b5e6-96231b3b80d8
* [LSR] Canonicalize reg1 + ... + regN into reg1 + ... + 1*regN.Quentin Colombet2014-05-20
| | | | | | | | | | | | | | | This commit introduces a canonical representation for the formulae. Basically, as soon as a formula has more that one base register, the scaled register field is used for one of them. The register put into the scaled register is preferably a loop variant. The commit refactors how the formulae are built in order to produce such representation. This yields a more accurate, but still perfectible, cost model. <rdar://problem/16731508> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209230 91177308-0d34-0410-b5e6-96231b3b80d8
* PR19767: DebugInfo emission of pointer constants.David Blaikie2014-05-20
| | | | | | | | | | | | | | | | | In refactoring DwarfUnit::isUnsignedDIType I restricted it to only work on values with signedness (unsigned or signed), asserting on anything else (which did uncover some bugs). But it turns out that we do need to emit constants of signless data, such as pointer constants - only null pointer constants are known to need this so far, but it's conceivable that there might be non-null pointer constants at some point (hardcoded address offsets for device drivers?). This patch just uses 'unsigned' for signless data such as pointer constants. Arguably we could use signless representations (DW_FORM_dataN) instead, allowing a trinary result from isUnsignedDIType (signed, unsigned, signless), but this seems reasonable for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209223 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoids DCE on write_registerRenato Golin2014-05-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209222 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] PR19796: Also match ISD::TargetConstant in isIntS16ImmediateAdam Nemet2014-05-20
| | | | | | | | | | | | | The SplitIndexingFromLoad changes exposed a latent isel bug in the PowerPC64 backend. We matched an immediate offset with STWX8 even though it only supports register offset. The culprit is the complex-pattern predicate, SelectAddrIdx, which decides that if the offset is not ISD::Constant it must be a register. Many thanks to Bill Schmidt for testing this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209219 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert: r209129 - [mips][mips64r6] Sorted *_ENC, *_DESC classes ↵Daniel Sanders2014-05-20
| | | | | | | | | | | | | | and tests After discussion with Zoran, we have decided to temporarily revert this commit. It's causing some difficult to resolve conflicts and we are under time pressure to deliver an initial MIPS64r6 compiler. We will re-apply an equivalent patch once the time pressure has passed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209211 91177308-0d34-0410-b5e6-96231b3b80d8
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