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* arm_neon.h now makes it through clang and generates appropriate code for ↵Nate Begeman2010-06-03
| | | | | | | | | those functions which can use generic vector operators rather than __builtin_neon_* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105380 91177308-0d34-0410-b5e6-96231b3b80d8
* arm_neon.h emitter now mostly complete for the purposes of initial testing.Nate Begeman2010-06-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105349 91177308-0d34-0410-b5e6-96231b3b80d8
* Pacify recent gcc: remove a pointless const qualifier.Duncan Sands2010-06-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105318 91177308-0d34-0410-b5e6-96231b3b80d8
* Checkpoint; handle 'int' and 'void' correctlyNate Begeman2010-06-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105316 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit full function prototypes. Definitions & typedefs to come.Nate Begeman2010-06-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105315 91177308-0d34-0410-b5e6-96231b3b80d8
* Checkpoint arm_neon.h generation with tablegenNate Begeman2010-06-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105307 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix commentSean Hunt2010-06-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105297 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow for creation of clang DeclNodes tables.Sean Hunt2010-05-30
| | | | | | | | The StmtNodes generator has been generalized to allow for the creation of DeclNodes tables as well, and another emitter was added for DeclContexts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105164 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit TargetRegisterInfo::composeSubRegIndices().Jakob Stoklund Olesen2010-05-28
| | | | | | Also verify that all subregister indices compose unambiguously. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105064 91177308-0d34-0410-b5e6-96231b3b80d8
* Comment out some code in prep for actual .td file checkpoint.Nate Begeman2010-05-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104927 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix build breakage.Eli Friedman2010-05-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104912 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to tablegen for auto-generating arm_neon.h from a tablegen ↵Nate Begeman2010-05-28
| | | | | | | | | | | | description of the intrinsics. The goal is to auto-generate both support for GCC-style (vector) and ARM-style (struct of vector) intrinsics. This is work in progress, but will be completed soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104910 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify raw_ostream usage.Dan Gohman2010-05-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104874 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor code simplification.Dan Gohman2010-05-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104845 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmMatcher: Ensure classes are totally ordered, so we can std::sort them ↵Daniel Dunbar2010-05-27
| | | | | | reliably. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104806 91177308-0d34-0410-b5e6-96231b3b80d8
* Check that inherited subregisters all have a direct SubRegIndex.Jakob Stoklund Olesen2010-05-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104755 91177308-0d34-0410-b5e6-96231b3b80d8
* Add StringRef::compare_numeric and use it to sort TableGen register records.Jakob Stoklund Olesen2010-05-26
| | | | | | | This means that our Registers are now ordered R7, R8, R9, R10, R12, ... Not R1, R10, R11, R12, R2, R3, ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104745 91177308-0d34-0410-b5e6-96231b3b80d8
* Suppress emmission of empty subreg/superreg/alias sets.Jakob Stoklund Olesen2010-05-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104741 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-26
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-26
| | | | | | This reverts commit 104654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-26
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop the SuperregHashTable. It is essentially the same as SubregHashTable.Jakob Stoklund Olesen2010-05-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
* Print symbolic SubRegIndex names on machine operands.Jakob Stoklund Olesen2010-05-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
* Ignore NumberHack and give each SubRegIndex instance a unique enum value ↵Jakob Stoklund Olesen2010-05-25
| | | | | | | | | | | instead. This passes lit tests, but I'll give it a go through the buildbots to smoke out any remaining places that depend on the old SubRegIndex numbering. Then I'll remove NumberHack entirely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104615 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
* diaggroup categories should take precedence over diag-specific groups.Chris Lattner2010-05-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104567 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-24
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the SubRegIndex TableGen class.Jakob Stoklund Olesen2010-05-24
| | | | | | | This is the beginning of purely symbolic subregister indices, but we need a bit of jiggling before the explicit numeric indices can be completely removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses ↵Daniel Dunbar2010-05-22
| | | | | | instead of just one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honorDaniel Dunbar2010-05-20
| | | | | | it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace FIRST_* and LAST_* macros with a generic STMT_RANGE macroSean Hunt2010-05-18
| | | | | | Also rename ABSTRACT to ABSTRACT_STMT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104018 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a QQQQ register file to model 4-consecutive Q registers.Evan Cheng2010-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding a v8i64 512-bit vector type. This will be used to model ARM NEON ↵Evan Cheng2010-05-13
| | | | | | intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103746 91177308-0d34-0410-b5e6-96231b3b80d8
* Update tablegen to generate shorts instead of chars for subgroup arrays.Chandler Carruth2010-05-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103704 91177308-0d34-0410-b5e6-96231b3b80d8
* Add initial kill flag support to FastISel.Dan Gohman2010-05-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103529 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes for Microsoft Visual Studio 2010, from Steven Watanabe!Douglas Gregor2010-05-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103457 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-06
| | | | | | | | | | and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-06
| | | | | | | doesn't have to guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a ↵Evan Cheng2010-05-06
| | | | | | coalescer bug that's fixed by 103170. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some stylistic issues with my last commit.Sean Hunt2010-05-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103164 91177308-0d34-0410-b5e6-96231b3b80d8
* Add newline to end of file to avoid warningShantonu Sen2010-05-05
| | | | | | | when building llvm with clang git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103084 91177308-0d34-0410-b5e6-96231b3b80d8
* Include the right header for toupperSean Hunt2010-05-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103073 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an emitter to handle the list of clang statement nodes.Sean Hunt2010-05-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103071 91177308-0d34-0410-b5e6-96231b3b80d8
* add the ability to associate 'category' names with clang diagnosticsChris Lattner2010-05-04
| | | | | | | | | | | and diagnostic groups. This allows the compiler to group diagnostics together (e.g. "Logic Warning", "Format String Warning", etc) like the static analyzer does. This is not exposed through anything in the compiler yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103050 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Matcher: Add support for over-riding the default MatchInstruction functionDaniel Dunbar2010-05-04
| | | | | | | name (for example, to allow targets to interpose the actual MatchInstruction function). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102987 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a pseudo instruction REG_SEQUENCE that takes a list of registers andEvan Cheng2010-05-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sub-register indices and outputs a single super register which is formed from a consecutive sequence of registers. This is used as register allocation / coalescing aid and it is useful to represent instructions that output register pairs / quads. For example, v1024, v1025 = vload <address> where v1024 and v1025 forms a register pair. This really should be modelled as v1024<3>, v1025<4> = vload <address> but it would violate SSA property before register allocation is done. Currently we use insert_subreg to form the super register: v1026 = implicit_def v1027 - insert_subreg v1026, v1024, 3 v1028 = insert_subreg v1027, v1025, 4 ... = use v1024 = use v1028 But this adds pseudo live interval overlap between v1024 and v1025. We can now modeled it as v1024, v1025 = vload <address> v1026 = REG_SEQUENCE v1024, 3, v1025, 4 ... = use v1024 = use v1026 After coalescing, it will be v1026<3>, v1025<4> = vload <address> ... = use v1026<3> = use v1026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes to edis that mark x86 call targets asSean Callanan2010-04-23
| | | | | | | memory operands rather than immediate operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102217 91177308-0d34-0410-b5e6-96231b3b80d8
* When doing Thumb disassembly, there's no need to consider ↵Johnny Chen2010-04-20
| | | | | | | | | t2ADDrSPi12/t2SUBrSPi12, as their generic counterparts t2ADDri12/t2SUBri12 should suffice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101929 91177308-0d34-0410-b5e6-96231b3b80d8
* stop computing InstImpInputs, it is deadChris Lattner2010-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101881 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGInstruction::ImpOperands is dead after my recent tblgen work, zap it.Chris Lattner2010-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101880 91177308-0d34-0410-b5e6-96231b3b80d8
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