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* Don't exit just because some early commands fail. Use the -k flag when ↵Bill Wendling2011-10-18
| | | | | | running the checks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142369 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VMOV.i64.Jim Grosbach2011-10-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.Jim Grosbach2011-10-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.Jim Grosbach2011-10-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON "vmov.i8" immediate assembly parsing and encoding.Jim Grosbach2011-10-17
| | | | | | | | | NEON immediates are "interesting". Start of the work to handle parsing them in an 'as' compatible manner. Getting the matcher to play nicely with these and the floating point immediates from VFP is an extra fun wrinkle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
* Forgot to add the project name to the 'svn ls' command.Bill Wendling2011-10-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142282 91177308-0d34-0410-b5e6-96231b3b80d8
* Add message to svn mkdir command.Bill Wendling2011-10-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142280 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix unused variable warning in the rare circumstance that we have no ↵Owen Anderson2011-10-17
| | | | | | feature-dependent instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142193 91177308-0d34-0410-b5e6-96231b3b80d8
* Pick low-hanging MatchEntry shrinkage fruit.Benjamin Kramer2011-10-17
| | | | | | Shaves 200k off Release-Asserts clang binaries on i386. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142191 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't download and compile compiler-rt, libcxx, and libcxxabi by default.Bill Wendling2011-10-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142185 91177308-0d34-0410-b5e6-96231b3b80d8
* Update to disable asserts. Build a phase 3 compiler, and compare phase 2 ↵Bill Wendling2011-10-17
| | | | | | files against phase 3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142173 91177308-0d34-0410-b5e6-96231b3b80d8
* Overhaul the 'test-release' script.Bill Wendling2011-10-16
| | | | | | | | This removes support for building llvm-gcc. It will eventually add support for building other projects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142165 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the tree before applying patch.Bill Wendling2011-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142155 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, ↵Craig Topper2011-10-16
| | | | | | VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
* Make SMDiagnostic a little more sane. Instead of passing around ↵Chris Lattner2011-10-16
| | | | | | | | | note/warning/error as a string, pass it around as an enum. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142107 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang ↵Chris Lattner2011-10-16
| | | | | | | | | | | | | | | | | does. Enhance the X86 asmparser to produce ranges in the one case that was annoying me, for example: test.s:10:15: error: invalid operand for instruction movl 0(%rax), 0(%edx) ^~~~~~~ It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use ranges where appropriate if someone is interested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142106 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper2011-10-16
| | | | | | 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a helper script to create branches and tag release candidates.Bill Wendling2011-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142098 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a script that helps merge changes into a release branch.Bill Wendling2011-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142097 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵Craig Topper2011-10-15
| | | | | | because these are the first VEX encoded instructions to use the reg field as an opcode extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix threads/jobs CalculationDavid Greene2011-10-14
| | | | | | | | Pass the correct jobs and threads information to the builder. We were underutilizing the number of jobs and threads specified by the user. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141977 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Helpful MessagesDavid Greene2011-10-14
| | | | | | | Bit just a bit more verbose about what's going on. Print options to make to aid debugging. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141976 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Option to Skip InstallDavid Greene2011-10-14
| | | | | | | Add a --no-install option to skip installing components. This speeds up the develop/test cycle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141975 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Option to Skip gcc BuildDavid Greene2011-10-14
| | | | | | | And a --no-gcc option to skip dragonegg and gcc builds. This greatly speeds up the develop/test cycle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141974 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 ANDN instruction. Including instruction selection.Craig Topper2011-10-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
* Ban rematerializable instructions with side effects.Jakob Stoklund Olesen2011-10-14
| | | | | | | | | | TableGen infers unmodeled side effects on instructions without a pattern. Fix some instruction definitions where that was overlooked. Also raise an error if a rematerializable instruction has unmodeled side effects. That doen't make any sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove extra semicolon.Eli Friedman2011-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141699 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-11
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit full ED initializers even for pseudo-instructions.Jakob Stoklund Olesen2011-10-10
| | | | | | This should unbreak the picky buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141575 91177308-0d34-0410-b5e6-96231b3b80d8
* Insert dummy ED table entries for pseudo-instructions.Jakob Stoklund Olesen2011-10-10
| | | | | | | | | | The table is indexed by opcode, so simply removing pseudo-instructions creates a wrong mapping from opcode to table entry. Add a test case for xorps which has a very high opcode that exposes this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach2011-10-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove MultidefsDavid Greene2011-10-07
| | | | | | | | | | | | | | | | | | | Multidefs are a bit unwieldy and incomplete. Remove them in favor of another mechanism, probably for loops. Revert "Make Test More Thorough" Revert "Fix a typo." Revert "Vim Support for Multidefs" Revert "Emacs Support for Multidefs" Revert "Document Multidefs" Revert "Add a Multidef Test" Revert "Update Test for Multidefs" Revert "Process Multidefs" Revert "Parser Multidef Support" Revert "Lexer Support for Multidefs" Revert "Add Multidef Data Structures" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141378 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert part of r141274. Only need to change encoding for xchg %eax, %eax in ↵Craig Topper2011-10-07
| | | | | | 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the Clang tblgen backends from LLVM.Peter Collingbourne2011-10-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141293 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This ↵Craig Topper2011-10-06
| | | | | | was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
* Build system infrastructure for multiple tblgens.Peter Collingbourne2011-10-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the TRI::getSubRegisterRegClass() hook.Jakob Stoklund Olesen2011-10-06
| | | | | | | | | | | | | | | | This restores my karma after I added TRI::getSubClassWithSubReg(). Register constraints are applied 'backwards'. Starting from the register class required by an instruction operand, the correct question is: 'How can I constrain the super-register register class so all its sub-registers satisfy the instruction constraint?' The getMatchingSuperRegClass() hook answers that. We never need to go 'forwards': Starting from a super-register register class, what register class are the sub-registers in? The getSubRegisterRegClass() hook did that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141258 91177308-0d34-0410-b5e6-96231b3b80d8
* Vim Support for MultidefsDavid Greene2011-10-05
| | | | | | Add vim highlighting support for multidefs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141238 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs Support for MultidefsDavid Greene2011-10-05
| | | | | | Add Emacs font-lock keyword support for multidefs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141237 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TRI::getSubClassWithSubReg(RC, Idx) function.Jakob Stoklund Olesen2011-10-05
| | | | | | | | | | | | | | | | This function is used to constrain a register class to a sub-class that supports the given sub-register index. For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD. The function will be used to compute register classes when emitting INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation of sub-register operations. The version provided by TableGen is usually adequate, but targets can override. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly use const_iterator.Jakob Stoklund Olesen2011-10-04
| | | | | | This should unbreak the Windows build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141105 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach TableGen to infer missing register classes.Jakob Stoklund Olesen2011-10-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The set of register classes should be closed under sub-register operations and intersections. That will allow the register allocator to model combinations of constraints accurately. This patch implements the easiest form of register class inference: For every register class, and for every sub-register SubIdx, the subset of registers in RC that have a SubIdx sub-register should also be a register class. This does create some new register classes for the targets in the tree: ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td file on purpose because it only has two registers. InstrEmitter and RegisterCoalescer have safeguards against selecting too small register classes, so it is harmless. PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32 sub-register of LR8. I think that might be an omission? X86 puts RIP in the GR64 class, and since that register doesn't have 8-bit sub-registers, we get: GR64_with_sub_8bit GR64_TC_with_sub_8bit GR64_NOREX_with_sub_8bit GR64_TC_with_sub_8bit_hi The various CodeGen classes have already been fixed so adding new register classes should not affect compile time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Store all allocation orders together.Jakob Stoklund Olesen2011-10-04
| | | | | | There is no need to keep the primary order separate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141082 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Privatize CodeGenRegisterClass::TheDef and Name.Jakob Stoklund Olesen2011-10-04
| | | | | | | | When TableGen starts creating its own register classes, the synthesized classes won't have a Record reference. All register classes must have a name, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Don't add synthetic Records to the RecordKeeper.Jakob Stoklund Olesen2011-10-04
| | | | | | | The RecordKeeper could be shared by multiple target instances, causing duplicate record errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141080 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-04
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove last references to hotpatch.Rafael Espindola2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141057 91177308-0d34-0410-b5e6-96231b3b80d8
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