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* Cosmetic changes, as per Nick's review.Devang Patel2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140785 91177308-0d34-0410-b5e6-96231b3b80d8
* Place this bracket according to the LLVM style.Duncan Sands2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140784 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Fix broken shared library buildJustin Holewinski2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140783 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand the x86 V_SET0* pseudos right after register allocation.Jakob Stoklund Olesen2011-09-29
| | | | | | | This also makes it possible to reduce the number of pseudo instructions and get rid of the encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140776 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/ARM: Unbreak! CMake! Build!NAKAMURA Takumi2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140774 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete NEONMoveFix, now unused.Jakob Stoklund Olesen2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140773 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ExecutionDepsFix instead of NEONMoveFix.Jakob Stoklund Olesen2011-09-29
| | | | | | | This enables NEON domain tracking across basic blocks, but should otherwise do the same thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140772 91177308-0d34-0410-b5e6-96231b3b80d8
* typo + pastoAndrew Trick2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140769 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NumImplicitOps which is now unused.Jakob Stoklund Olesen2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140767 91177308-0d34-0410-b5e6-96231b3b80d8
* LSR: rewrite inner loops only.Andrew Trick2011-09-29
| | | | | | | | | Rewriting the entire loop nest now requires -enable-lsr-nested. See PR11035 for some performance data. A few unit tests specifically test nested LSR, and are now under a flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140762 91177308-0d34-0410-b5e6-96231b3b80d8
* Move to ISelLowering.Bill Wendling2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140754 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Add new patterns for bitconvert and any_extendJustin Holewinski2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140753 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the local we already set up.Eric Christopher2011-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140745 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.Jakob Stoklund Olesen2011-09-29
| | | | | | | | | | | | | | | | | | | | | | | The function needs to scan the implicit operands anyway, so no performance is won by caching the number of implicit operands added to an instruction. This also fixes a bug when adding operands after an implicit operand has been added manually. The NumImplicitOps count wasn't kept up to date. MachineInstr::addOperand() will now consistently place all explicit operands before all the implicit operands, regardless of the order they are added. It is possible to change an MI opcode and add additional explicit operands. They will be inserted before any existing implicit operands. The only exception is inline asm instructions where operands are never reordered. This is because of a hack that marks explicit clobber regs on inline asm as <implicit-def> to please the fast register allocator. This hack can go away when InstrEmitter and FastIsel can add exact <dead> flags to physreg defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140744 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r140731, "Define classes for unary and binary FP instructions and use ↵Jakob Stoklund Olesen2011-09-28
| | | | | | | | them to define" It broke the unit tests. Please reapply with tests fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140735 91177308-0d34-0410-b5e6-96231b3b80d8
* Tighten a ARM dag combine condition to avoid an identity transformation, whichEvan Cheng2011-09-28
| | | | | | | | | ends up introducing a cycle in the DAG. rdar://10196296 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
* Define classes for unary and binary FP instructions and use them to defineAkira Hatanaka2011-09-28
| | | | | | | multiclasses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140731 91177308-0d34-0410-b5e6-96231b3b80d8
* Have the SjLjEHPrepare pass do some more heavy lifting.Bill Wendling2011-09-28
| | | | | | | | | Upon further review, most of the EH code should remain written at the IR level. The part which breaks SSA form is the dispatch table, so that part will be moved to the back-end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140730 91177308-0d34-0410-b5e6-96231b3b80d8
* PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU ↵Eli Friedman2011-09-28
| | | | | | does not support them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140723 91177308-0d34-0410-b5e6-96231b3b80d8
* Object: Add isSection{Data,BSS}.Michael J. Spencer2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140721 91177308-0d34-0410-b5e6-96231b3b80d8
* Perform the lowering only if there are invokes.Bill Wendling2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140719 91177308-0d34-0410-b5e6-96231b3b80d8
* Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.Bill Wendling2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140718 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Fix alignment logicJustin Holewinski2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140709 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.Akira Hatanaka2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140705 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove definitions of branch-on-FP-likely instructions. They are deprecated.Akira Hatanaka2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140704 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips64 predicate definitions. Patch by Liu.Akira Hatanaka2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140703 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars: generalize SCEV getPreStartForSignExtend.Andrew Trick2011-09-28
| | | | | | | | Handle general Add expressions to avoid leaving around redundant 32-bit IVs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140701 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: MC-ize the PTX backend (patch 2 of N)Justin Holewinski2011-09-28
| | | | | | Get rid of some of the no-longer-needed parts of PTXAsmPrinter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140698 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: MC-ize the PTX back-end (patch 1 of N)Justin Holewinski2011-09-28
| | | | | | | | Lay some groundwork for converting to MC-based asm printer. This is the first of probably many patches to bring the back-end back up-to-date with all of the recent MC changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140697 91177308-0d34-0410-b5e6-96231b3b80d8
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-28
| | | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
* A typeid of zero means a cleanup, not a catch. This case occursDuncan Sands2011-09-28
| | | | | | | when there is both a catch and a cleanup. Correct the comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140686 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Simplify code. No functionality change.Benjamin Kramer2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140680 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Pass param name strings per const reference.Benjamin Kramer2011-09-28
| | | | | | The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140679 91177308-0d34-0410-b5e6-96231b3b80d8
* Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.Bill Wendling2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140678 91177308-0d34-0410-b5e6-96231b3b80d8
* Bitcast the alloca to an i8* to match the intrinsic's signature.Bill Wendling2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140677 91177308-0d34-0410-b5e6-96231b3b80d8
* Create and use an llvm.eh.sjlj.functioncontext intrinsic.Bill Wendling2011-09-28
| | | | | | | | | This intrinsic is used to pass the index of the function context to the back-end for further processing. The back-end is in charge of filling in the rest of the entries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140676 91177308-0d34-0410-b5e6-96231b3b80d8
* In the new EH model, setup the function context and the call site info.Bill Wendling2011-09-28
| | | | | | | | | | | | | The DWARF exception pass uses the call site information, which is set up here. A pre-RA pass is too late for it to use this information. So create and setup the function context here, and then insert the call site values here (and map the call sites for the DWARF EH pass). This is simpler than the original pass, and doesn't make the CFG lose its SSA-ness. It's a win-win-win-win-lose-win-win situation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140675 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't conditionalize execution of the SjLj EH prepare pass.Bill Wendling2011-09-28
| | | | | | | | We may need an SjLj EH preparation pass for some call site information, at least in the short term. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140674 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars should hoist [sz]ext because licm is not rerun.Andrew Trick2011-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140670 91177308-0d34-0410-b5e6-96231b3b80d8
* PR10628: Fix getModRefInfo so it queries the underlying alias() ↵Eli Friedman2011-09-28
| | | | | | implementation correctly while checking nocapture calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140666 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename class and clean up source.Jakob Stoklund Olesen2011-09-28
| | | | | | No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140664 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.Jakob Stoklund Olesen2011-09-28
| | | | | | I'll clean up the source in the next commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140663 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove MipsFPRound. Mips1 is no longer supported.Akira Hatanaka2011-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140661 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove X86-dependent stuff from SSEDomainFix.Jakob Stoklund Olesen2011-09-27
| | | | | | | | | This also enables domain swizzling for AVX code which required a few trivial test changes. The pass will be moved to lib/CodeGen shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140659 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak CMake build.Ted Kremenek2011-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140655 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement TII::get/setExecutionDomain() for ARM.Jakob Stoklund Olesen2011-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140653 91177308-0d34-0410-b5e6-96231b3b80d8
* Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.Jakob Stoklund Olesen2011-09-27
| | | | | | | | I am going to unify the SSEDomainFix and NEONMoveFix passes into a single target independent pass. They are essentially doing the same thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140652 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.Jim Grosbach2011-09-27
| | | | | | | | | Add inst alias to handle these assembly forms. Add tests, too. rdar://10178799 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8
* This is the start of the new SjLj EH preparation pass, which will replace theBill Wendling2011-09-27
| | | | | | | | | | | | | | | | | | | | current IR-level pass. The old SjLj EH pass has some problems, especially with the new EH model. Most significantly, it violates some of the new restrictions the new model has. For instance, the 'dispatch' table wants to jump to the landing pad, but we cannot allow that because only an invoke's unwind edge can jump to a landing pad. This requires us to mangle the code something awful. In addition, we need to keep the now dead landingpad instructions around instead of CSE'ing them because the DWARF emitter uses that information (they are dead because no control flow edge will execute them - the control flow edge from an invoke's unwind is superceded by the edge coming from the dispatch). Basically, this pass belongs not at the IR level where SSA is king, but at the code-gen level, where we have more flexibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140646 91177308-0d34-0410-b5e6-96231b3b80d8
* Embed patterns in definitions of MFC1 and MTC1 instead of defining them outsideAkira Hatanaka2011-09-27
| | | | | | | of the instruction definitions using Pat<>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140644 91177308-0d34-0410-b5e6-96231b3b80d8
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