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path: root/test/CodeGen/R600/fmul.ll
Commit message (Expand)AuthorAge
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-10
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-04
* R600: Expand vector float operations for both SI and R600Tom Stellard2013-08-16
* R600: Set scheduling preference to Sched::SourceTom Stellard2013-08-12
* R600: Add 64-bit float load/store supportTom Stellard2013-08-01
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-31
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-31
* R600: Schedule copy from phys register at beginning of blockVincent Lejeune2013-06-05
* R600: use capital letter for PV channelVincent Lejeune2013-06-03
* R600: Use bottom up scheduling algorithmVincent Lejeune2013-05-17
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-02
* R600: Reorganize lit tests and document how they should be organizedTom Stellard2013-04-19
* Add R600 backendTom Stellard2012-12-11
* Revert "test/CodeGen/R600: Add some basic tests v6"Tom Stellard2012-07-16
* test/CodeGen/R600: Add some basic tests v6Tom Stellard2012-07-16