summaryrefslogtreecommitdiff
path: root/test/MC
Commit message (Collapse)AuthorAge
* AArch64: print relocation addends if present on AArch64Tim Northover2013-06-17
| | | | | | | llvm-objdump should provide some way of printing out the addends present in the .rela sections for debugging purposes if nothing else. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184072 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix thumb coprocessor instruction with pre-writeback disassemblyAmaury de la Vieuville2013-06-14
| | | | | | | was stc2 p0, c0, [r0]! instead of stc2 p0, c0, [r0,#0]! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183975 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix B decodingAmaury de la Vieuville2013-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183914 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix t2am_imm8_offset operand printing for imm=#-0Amaury de la Vieuville2013-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183913 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Make the cmov aliases work with intel syntax too.Benjamin Kramer2013-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183907 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC/DWARF] Support .debug_frame / .debug_line code alignment factorsUlrich Weigand2013-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | I've been comparing the object file output of LLVM's integrated assembler against the external assembler on PowerPC, and one area where differences still remain are in DWARF sections. In particular, the GNU assembler generates .debug_frame and .debug_line sections using a code alignment factor of 4, since all PowerPC instructions have size 4 and must be aligned to a multiple of 4. However, current MC code hard-codes a code alignment factor of 1. This patch changes this by adding a "minimum instruction alignment" data element to MCAsmInfo and using this as code alignment factor. This requires passing a MCContext into MCDwarfLineAddr::Encode and MCDwarfLineAddr::EncodeAdvanceLoc. Note that one caller, MCDwarfLineAddr::Write, didn't actually have that information available. However, it turns out that this routine is in fact never used in the whole code base, so the patch simply removes it. If it turns out to be needed again at a later time, it could be re-added with an updated interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183834 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Use assembler source in MC testsUlrich Weigand2013-06-12
| | | | | | | | | | | | | | A couple of old test cases in test/MC/PowerPC were still using LLVM IR. Now that we have a working assembler, we can move them to assembler tests instead: ppc64-initial-cfa.ll ppc64-relocs-01.ll ppc64-tls-relocs-01.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183829 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework r183728, suppress assert(0) for now. Its behavior depends on ↵NAKAMURA Takumi2013-06-11
| | | | | | | | assertions on win32 hosts. FIXME: Introduce yet another checker but assert(0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183736 91177308-0d34-0410-b5e6-96231b3b80d8
* It adds support for negative zero offsets for loads and stores.Mihai Popa2013-06-11
| | | | | | | Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value. Behavior already present for Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183734 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These ↵Mihai Popa2013-06-11
| | | | | | are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183733 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Enforce decoding rules for VLDn instructionsAmaury de la Vieuville2013-06-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183731 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix STREX/LDREX reecodingAmaury de la Vieuville2013-06-11
| | | | | | The decoded MCInst wasn't reencoded as the same instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183729 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak a couple of tests on win32 hosts with +Asserts.NAKAMURA Takumi2013-06-11
| | | | | | | | | - Don't use assert(0), or tests may pass or fail according to assertions. - For now, The tests are marked as XFAIL for win32 hosts. FIXME: Could we avoid XFAIL to specify triple in the RUN lines? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183728 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.Tim Northover2013-06-10
| | | | | | | | | | | Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some only support Thumb mode (M-class ones currently). This makes sure such CPUs default to the correct mode and makes the AsmParser diagnose an attempt to switch modes incorrectly. rdar://14024354 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183710 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support extended sc mnemonicUlrich Weigand2013-06-10
| | | | | | | | | | | A plain "sc" without argument is supposed to be treated like "sc 0" by the assembler. This patch adds a corresponding alias. Problem reported by Joerg Sonnenberger. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183687 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support branch mnemonics with implied CR0Ulrich Weigand2013-06-10
| | | | | | | | | | | | The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183686 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-10
| | | | | | ISB should only accepts full system sync, other options are reserved git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM unwind opcode assembler in several cases.Logan Chien2013-06-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes to ARM unwind opcode assembler: * Fix multiple .save or .vsave directives. Besides, the order is preserved now. * For the directives which will generate multiple opcodes, such as ".save {r0-r11}", the order of the unwind opcode is fixed now, i.e. the registers with less encoding value are popped first. * Fix the $sp offset calculation. Now, we can use the .setfp, .pad, .save, and .vsave directives at any order. Changes to test cases: * Add test cases to check the order of multiple opcodes for the .save directive. * Fix the incorrect $sp offset in the test case. The stack pointer offset specified in the test case was incorrect. (Changed test cases: ehabi-mc-section.ll and ehabi-mc.ll) * The opcode to restore $sp are slightly reordered. The behavior are not changed, and the new output is same as the output of GNU as. (Changed test cases: eh-directive-pad.s and eh-directive-setfp.s) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183627 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix VMOVvnf32 decoding when ambiguous with VCVTAmaury de la Vieuville2013-06-08
| | | | | | Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183612 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: enforce SRS decoding constraintsAmaury de la Vieuville2013-06-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183611 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-08
| | | | | | | | | Handle the case when the disassembler table can't tell the difference between some encodings of QADD and CPS. Add some necessary safe guards in CPS decoding as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183610 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix VCVT decodingAmaury de la Vieuville2013-06-08
| | | | | | UNPRED was reported instead of UNDEF git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183608 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't hide the first ELF symbol.Rafael Espindola2013-06-05
| | | | | | | | The first symbol on ELF is dummy, but it has a defined content and readelf normally displays it. With this change llvm-readobj also displays it and we can check that llvm-mc output is correct according to the standard. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183337 91177308-0d34-0410-b5e6-96231b3b80d8
* This is a simple patch that changes RRX and RRXS to accept all registers as ↵Mihai Popa2013-06-05
| | | | | | | | operands. According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: permit upper-case BE/LE on setend instructionTim Northover2013-05-31
| | | | | | Patch by Amaury de la Vieuville. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183012 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-31
| | | | | | | | | These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183011 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix VEXT encoding corner caseTim Northover2013-05-31
| | | | | | | | | | The disassembly of VEXT instructions was too lax in the bits checked. This fixes the case where the instruction affects Q-registers but a misaligned lane was specified (should be UNDEFINED). Patch by Amaury de la Vieuville git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8
* Change how we iterate over relocations on ELF.Rafael Espindola2013-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | For COFF and MachO, sections semantically have relocations that apply to them. That is not the case on ELF. In relocatable objects (.o), a section with relocations in ELF has offsets to another section where the relocations should be applied. In dynamic objects and executables, relocations don't have an offset, they have a virtual address. The section sh_info may or may not point to another section, but that is not actually used for resolving the relocations. This patch exposes that in the ObjectFile API. It has the following advantages: * Most (all?) clients can handle this more efficiently. They will normally walk all relocations, so doing an effort to iterate in a particular order doesn't save time. * llvm-readobj now prints relocations in the same way the native readelf does. * probably most important, relocations that don't point to any section are now visible. This is the case of relocations in the rela.dyn section. See the updated relocation-executable.test for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182908 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Immediate compare-and-branch supportRichard Sandiford2013-05-29
| | | | | | | This patch adds support for the CIJ and CGIJ instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182846 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips assembler: Improve set register alias handlingJack Carter2013-05-28
| | | | | | | | | | | | | | | | | This patch solves the problem of numeric register values not being accepted: ../set_alias.s:1:11: error: expected valid expression after comma .set r4,$4 ^ The parsing of .set directive is changed and handling of symbols in code as well to enable this feature. The test example is added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182807 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Register compare-and-branch supportRichard Sandiford2013-05-28
| | | | | | | | | | | | | | | This patch adds support for the CRJ and CGRJ instructions. Support for the immediate forms will be a separate patch. The architecture has a large number of comparison instructions. I think it's generally better to concentrate on using the "best" comparison instruction first and foremost, then only use something like CRJ if CR really was the natual choice of comparison instruction. The patch therefore opportunistically converts separate CR and BRC instructions into a single CRJ while emitting instructions in ISelLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182764 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for DWARF line number table entries for values in the instructionCameron Zwarich2013-05-25
| | | | | | stream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182712 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Improve AsmParser handling of invalid instructionsRichard Sandiford2013-05-24
| | | | | | | | | | | | | | | | | | | | | | | | Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182644 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Improve AsmParser register parsingRichard Sandiford2013-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea is to make sure that: (1) "register expected" is restricted to cases where ParseRegister() is called and the token obviously isn't a register. (2) "invalid register" is restricted to cases where a register-like "%..." sequence is found, but the "..." makes no sense. (3) the generic "invalid operand for instruction" is used in cases where the wrong register type is used (GPR instead of FPR, etc.). (4) the new "invalid register pair" is used if the register has the right type, but is not a valid register pair. Testing of (1)-(3) is now restricted to regs-bad.s. It uses a representative instruction for each register class to make sure that only registers from that class are accepted. (4) is tested by both regs-bad.s (which checks all invalid register pairs) and insn-bad.s (which tests one invalid pair for each instruction that requires a pair). While there, I changed "Number" to "Num" for consistency with the operand class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182643 91177308-0d34-0410-b5e6-96231b3b80d8
* VSTn instructions have a number of encoding constraints which are not ↵Mihai Popa2013-05-20
| | | | | | implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182281 91177308-0d34-0410-b5e6-96231b3b80d8
* Q registers are encoded in fields of the same length as D registers. As Q ↵Mihai Popa2013-05-20
| | | | | | registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182279 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Merge/rename PPC fixup typesUlrich Weigand2013-05-17
| | | | | | | | | | | | | | | | Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly the same everywhere, it no longer makes sense to have two fixup types. This patch merges them both into a single type fixup_ppc_half16, and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency. (The half16 and half16ds names are taken from the description of relocation types in the PowerPC ABI.) No change in code generation expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182092 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Fix processing of ha16/lo16 fixupsUlrich Weigand2013-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current PowerPC MC back end distinguishes between fixup_ppc_ha16 and fixup_ppc_lo16, which are determined by the instruction the fixup applies to, and uses this distinction to decide whether a fixup ought to resolve to the high or the low part of a symbol address. This isn't quite correct, however. It is valid -if unusual- assembler to use, e.g. li 1, symbol@ha or lis 1, symbol@l Whether the high or the low part of the address is used depends solely on the @ suffix, not on the instruction. In addition, both li 1, symbol and lis 1, symbol are valid, assuming the symbol address fits into 16 bits; again, both will then refer to the actual symbol value (so li will load the value itself, while lis will load the value shifted by 16). To fix this, two places need to be adapted. If the fixup cannot be resolved at assembler time, a relocation needs to be emitted via PPCELFObjectWriter::getRelocType. This routine already looks at the VK_ type to determine the relocation. The only problem is that will reject any _LO modifier in a ha16 fixup and vice versa. This is simply incorrect; any of those modifiers ought to be accepted for either fixup type. If the fixup *can* be resolved at assembler time, adjustFixupValue currently selects the high bits of the symbol value if the fixup type is ha16. Again, this is incorrect; see the above example lis 1, symbol Now, in theory we'd have to respect a VK_ modifier here. However, in fact common code never even attempts to resolve symbol references using any nontrivial VK_ modifier at assembler time; it will always fall back to emitting a reloc and letting the linker handle it. If this ever changes, presumably there'd have to be a target callback to resolve VK_ modifiers. We'd then have to handle @ha etc. there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182091 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips assembler: Add TwoOperandConstraint definitionsJack Carter2013-05-16
| | | | | | | | | | | | | | | | This patch removes alias definition for addiu $rs,$imm and instead uses the TwoOperandAliasConstraint field in the ArithLogicI instruction class. This way all instructions that inherit ArithLogicI class have the same macro defined. The usage examples are added to test files. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182048 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips assembler: Add branch macro definitionsJack Carter2013-05-16
| | | | | | | | | | | | | This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows: bnez $rs,$imm => bne $rs,$zero,$imm beqz $rs,$imm => beq $rs,$zero,$imm The corresponding test cases are added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Remove need for adjustFixupOffst hackUlrich Weigand2013-05-15
| | | | | | | | | | | | | | | | | | Now that applyFixup understands differently-sized fixups, we can define fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte fixups, applied at an offset of 2 relative to the start of the instruction text. This has the benefit that if we actually need to generate a real relocation record, its address will come out correctly automatically, without having to fiddle with the offset in adjustFixupOffset. Tested on both 64-bit and 32-bit PowerPC, using external and integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181894 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Make use of SUBTRACT HALFWORDRichard Sandiford2013-05-15
| | | | | | | Thanks to Ulrich Weigand for noticing that this instruction was missing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181893 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add test case for r181891Ulrich Weigand2013-05-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181892 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Consolidate disassembler tests for valid input into 2 big testsRichard Sandiford2013-05-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181879 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Consolidate assembler tests into 4 big testsRichard Sandiford2013-05-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181878 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the PowerPC system call (sc) instruction.Bill Schmidt2013-05-14
| | | | | | | Instruction added at request of Roman Divacky. Tested via asm-parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181821 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM FastISel tests, as a first step to enabling ARM FastISelDerek Schuff2013-05-14
| | | | | | | | | | | | | | | | | | | | | ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181801 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add disassembler supportRichard Sandiford2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181777 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add extra testscases for r181773Richard Sandiford2013-05-14
| | | | | | | Forgot to svn add these... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181774 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Rework handling of constant PC-relative operandsRichard Sandiford2013-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GNU assembler treats things like: brasl %r14, 100 in the same way as: brasl %r14, .+100 rather than as a branch to absolute address 100. We implemented this in LLVM by creating an immediate operand rather than the usual expr operand, and by handling immediate operands specially in the code emitter. This was undesirable for (at least) three reasons: - the specialness of immediate operands was exposed to the backend MC code, rather than being limited to the assembler parser. - in disassembly, an immediate operand really is an absolute address. (Note that this means reassembling printed disassembly can't recreate the original code.) - it would interfere with any assembly manipulation that we might try in future. E.g. operations like branch shortening can change the relative position of instructions, but any code that updates sym+offset addresses wouldn't update an immediate "100" operand in the same way as an explicit ".+100" operand. This patch changes the implementation so that the assembler creates a "." label for immediate PC-relative operands, so that the operand to the MCInst is always the absolute address. The patch also adds some error checking of the offset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181773 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-11 08:43:57 +0000