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* XOP instructions and encoding tests.Jan Sjödin2011-12-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146407 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for gnu_indirect_function.Roman Divacky2011-12-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146377 91177308-0d34-0410-b5e6-96231b3b80d8
* Manually upgrade the test suite to specify the flag to cttz and ctlz.Chandler Carruth2011-12-12
| | | | | | | | | | | | | | | | | | | | | | | I followed three heuristics for deciding whether to set 'true' or 'false': - Everything target independent got 'true' as that is the expected common output of the GCC builtins. - If the target arch only has one way of implementing this operation, set the flag in the way that exercises the most of codegen. For most architectures this is also the likely path from a GCC builtin, with 'true' being set. It will (eventually) require lowering away that difference, and then lowering to the architecture's operation. - Otherwise, set the flag differently dependending on which target operation should be tested. Let me know if anyone has any issue with this pattern or would like specific tests of another form. This should allow the x86 codegen to just iteratively improve as I teach the backend how to differentiate between the two forms, and everything else should remain exactly the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146370 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an explicit test of the auto-upgrade functionality for the newChandler Carruth2011-12-12
| | | | | | | | | | | | | intrinsic syntax. Now that this is explicitly covered, I plan to upgrade the existing test suite to use an explicit immediate. Note that I plan to specify 'true' in most places rather than the auto-upgraded value as that is the far more common value to end up here as that is the value coming from GCC's builtins. The only place I'm likely to put a 'false' in is when testing x86 which actually has different instructions for the two variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146369 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the verifier to reject all non-constant arguments to the secondChandler Carruth2011-12-12
| | | | | | argument of the cttz and ctlz intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146360 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-11
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146341 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't assume things about the exact details of the LLVM version number,Chandler Carruth2011-12-10
| | | | | | such as what VCS information is attached. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146333 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert associate SelectInsertValue test as well.Chad Rosier2011-12-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146332 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r146322 to appease buildbots. Original commit message:Chad Rosier2011-12-10
| | | | | | | | | Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146328 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-10
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146322 91177308-0d34-0410-b5e6-96231b3b80d8
* Make CR spill and restore use a reserved register. These operations cannot ↵Hal Finkel2011-12-10
| | | | | | use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146318 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gasRafael Espindola2011-12-10
| | | | | | | | does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC, but it doesn't change the immediate in the same way as when the expression has no right hand side symbol. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146311 91177308-0d34-0410-b5e6-96231b3b80d8
* Splats can contain undef's; make sure to handle them correctly. PR11526.Eli Friedman2011-12-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146299 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly aliases for BIC<-->AND (immediate).Jim Grosbach2011-12-09
| | | | | | | | | | | | When the immediate operand of an AND or BIC instruction isn't representable in the immediate field of the instruction, but the bitwise negation of the immediate is, assemble the instruction as the inverse operation instead with the inverted immediate as the operand. rdar://10550057 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
* Update test to something more sensible.Evan Cheng2011-12-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146282 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-09
| | | | | | | | | | | | Refactor the instructions into fixed writeback and register-stride writeback variants to simplify the offset operand (no more optional register operand using reg0). This is a simpler representation and allows the assembly parser to more easily handle these instructions. Add tests for the instruction variants now supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for selecting insertvalue.Chad Rosier2011-12-09
| | | | | | rdar://10530851 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146276 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle reloc_signed_4byte in here. Not doing so was a regression from myRafael Espindola2011-12-09
| | | | | | | previous commit. It is strange that we see it in 32 bits. We already have a fixme about it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146273 91177308-0d34-0410-b5e6-96231b3b80d8
* The second part of support for generating dwarf for assembly source files. ThisKevin Enderby2011-12-09
| | | | | | | | | | | generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each non-temporary label. The next part will be to get the clang driver to enable this when assembling a .s file. rdar://9275556 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146262 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Add patterns for the various rounding ops for SSE4.1 and AVX.Benjamin Kramer2011-12-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146257 91177308-0d34-0410-b5e6-96231b3b80d8
* Add -unroll-runtime for unrolling loops with run-time trip counts.Andrew Trick2011-12-09
| | | | | | | | | | | | | | Patch by Brendon Cahoon! This extends the existing LoopUnroll and LoopUnrollPass. Brendon measured no regressions in the llvm test suite with -unroll-runtime enabled. This implementation works by using the existing loop unrolling code to unroll the loop by a power-of-two (default 8). It generates an if-then-else sequence of code prior to the loop to execute the extra iterations before entering the unrolled loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146245 91177308-0d34-0410-b5e6-96231b3b80d8
* Forgot setting -march.Evan Cheng2011-12-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146244 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in aRafael Espindola2011-12-09
| | | | | | | | symbol difference. This matches gas behavior and fixes PR11513. We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146238 91177308-0d34-0410-b5e6-96231b3b80d8
* jalr should use t9 ($25) for indirect calls regardless of the relocation modelAkira Hatanaka2011-12-09
| | | | | | | | specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146229 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.Eli Friedman2011-12-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146219 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix infinite loop in DSE when deleting a free in a reachable loop that's alsoNick Lewycky2011-12-08
| | | | | | | trivially infinite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146197 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417Evan Cheng2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146196 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VSHR implied destination operand form aliases.Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
* Add various missing AVX patterns which was causing crashes. Sadly, the generatedEvan Cheng2011-12-08
| | | | | | | | | code looks pretty bad compared to SSE. rdar://10538793 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146191 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up a bit.Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146190 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VSUB implied destination operand form aliases.Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up a bit.Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146181 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VQADD implied destination operand form aliases.Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM a few more VMUL implied destination operand form aliases.Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach SelectionDAG to match more calls to libm functions onto existing ↵Owen Anderson2011-12-08
| | | | | | SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146171 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test for r146163.Evan Cheng2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146167 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsicsDaniel Dunbar2011-12-08
| | | | | | | sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).", it is failing tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146157 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/vec_compare-2.ll: Add explicit -mtriple=i686-linux.NAKAMURA Takumi2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146152 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the integer-promotion of bitcast operations on vector types.Nadav Rotem2011-12-08
| | | | | | | | | We must not issue a bitcast operation for integer-promotion of vector types, because the location of the values in the vector may be different. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146150 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-08
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146143 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON two-operand aliases for VSHL(immediate).Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON two-operand aliases for VSHL(register).Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM optional destination operand variants for VEXT instructions.Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up.Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146113 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.Jim Grosbach2011-12-07
| | | | | | For 'gas' compatibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
* 32 to 64-bit zext pattern.Akira Hatanaka2011-12-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146096 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM two-operand aliases for VAND/VEOR/VORR instructions.Jim Grosbach2011-12-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM two-operand aliases for VADDW instructions.Jim Grosbach2011-12-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
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